TS68040 ATMEL Corporation, TS68040 Datasheet - Page 10

• Manufacturer Part Number: TS68040
• Description: 32-bit Mpu, 25-33 MHZ
• Manufacturer: ATMEL Corporation

10/38
Thermal device characteristics
The TS 68040 presents some inherent characteristics which should be considered when evaluating a method of cooling the
device. The following paragraphs discuss these die / package and power considerations.
Die and package
The TS 68040 is being placed in a cavity-down alumina-ceramic 179-pin PGA that has a specified thermal resistance from
junction to case of 1°C/W. This package differs from previous TS 68000 Family PGA packages which were cavity up. This
cavity-down design allows the die to be attached to the top surface of the package, which increases the ability of the part
to dissipate heat through the package surface or an attached heat sink. The maximum perimeter that the TS 68040 allows
for a heat sink on its surface without interfering with the capacitor pads is 1.48"
of the particular heat sink will need to be determined by the system designer considering both thermal performance requi-
rements and size requirements.
Power considerations
The TS 68040 has a maximum power rating, which varies depending on the operating frequency and the output buffer mode
combination being used. The large buffer output mode dissipates more power than the small, and the higher frequencies of
operation dissipate more power than the lower frequencies. The following paragraphs discuss tradeoffs in using the different
output buffer modes, calculation of specific maximum power dissipation for different modes, and the relationship of thermal
resistances and temperatures.
Output buffer mode
The 68040 is capable of resetting to enable for a combination of either large buffers or small buffers on the outputs of the
miscellaneous control signals, data bus, and address bus / transfer attribute pins. The large buffers offer quicker output times,
which allow for an easier logic design. However, they do so by driving about 11 times as much current as the small buffers
(refer to TS 68040 Electrical specifications for current output). The designer should consider whether the quicker timings
present enough advantage to justify the additional consideration to the individual signal terminations, the die power con-
sumption, and the required cooling for the device. Since the TS 68040 can be powered-up in one of eight output buffer
modes upon reset, the actual maximum power consumption for TS 68040 rated at a particular maximum operating frequency
is dependent upon the power up mode. Therefore, the TS 68040 is rated at a maximum power dissipation for either the large
buffers or small buffers at a particular frequency (refer to TS 68040 Electrical specifications). This allows the possibility of
some of the thermal management to be controlled upon reset. The following equation provides a rough method to calculate
the maximum power consumption for a chosen output buffer mode :
where :
P D
P DSB
P DLB
PINS LB
PINS CLB = Number of pins capable of the large buffer mode
Table 6 shows the simplified relationship on the maximum power dissipation for eight possible configurations of output buffer
modes.
Table 6 - Maximum power dissipation for output buffer mode configurations
To calculate the specific power dissipation of a specific design, the termination method of each signal must be considered.
For example, a signal output that is not connected would not dissipate any additional power if it were configured in the large
buffer rather than the small buffer mode.
Small buffer
Small buffer
Small buffer
Small buffer
Large buffer
Large buffer
Large buffer
Large buffer
Data bus
= Max. power dissipation for output buffer mode selected
= Max. power dissipation for small buffer mode (all outputs)
= Max. power dissipation for large buffer mode (all outputs)
= Number of pins large buffer mode
Small buffer
Small buffer
Large buffer
Large buffer
Small buffer
Small buffer
Large buffer
Large buffer
Output configuration
P D
Address bus and
transfer attrib.
P DSB
P DLB – P DSB
Small buffer
Large buffer
Small buffer
Large buffer
Small buffer
Large buffer
Small buffer
Large buffer
Misc. control signals
PINS LB PINS CLB
1.48". The specific dimensions and design
P DSB
P DSB
P DSB
P DSB
P DSB
P DSB
P DSB
P DSB
Maximum power dissipation
P DLB – P DSB
P DLB – P DSB
P DLB – P DSB
P DLB – P DSB
P DLB – P DSB
P DLB – P DSB
P DLB – P DSB
P D
(Equation 4.1)
13 %
52 %
65 %
35 %
48 %
87 %
100 %