TSPC603RVGH8LC Atmel, TSPC603RVGH8LC Datasheet - Page 42

• Manufacturer Part Number: TSPC603RVGH8LC
• Description: IC MPU 32BIT 8MHZ 255CBGA
• Manufacturer: Atmel

Specifications of TSPC603RVGH8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

12.4.3
42
TSPC603R
Instruction Timing
The 603R’s TLBs are 64-entry, 2-way set-associative caches that contain instruction and data
address translations. The 603R provides hardware assistance for software table search opera-
tions through the ashed page table on the TLB misses. The supervisor software can invalidate
TLB entries selectively.
The 603R also provides independent four-entry BAT arrays for instructions and data that main-
tain address translations for blocks of memory. These entries define blocks that can vary from
128 Kbytes to 256 Mbytes. The BAT arrays are maintained by system software.
As specified by the PowerPC architecture, the hashed page table is a variable-sized data struc-
ture that defines the mapping between virtual page numbers and physical page numbers. The
page table size is a power of 2, and its starting address is a multiple of its size.
Also as specified by the PowerPC architecture, the page table contains a number of Page Table
Entry Groups (PTEGs). A PTEG contains eight Page Table Entries (PTEs) of eight bytes each;
therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for table search
operations.
The 603R is a pipelined superscalar processor. A pipelined processor is one in which the pro-
cessing of an instruction is reduced into discrete stages. Because the processing of an
instruction is broken into a series of stages, an instruction does not require the entire resources
of an execution unit. For example, after an instruction completes the decode stage, it can pass
on to the next stage, while the subsequent instruction can advance into the decode stage. This
improves the throughput of the instruction flow. For example, it may take three cycles for a float-
ing-point instruction to complete, but if there are no stalls in the floating-point pipeline, a series of
floating-point instructions can have a throughput of one instruction per cycle.
The instruction pipeline in the 603R has four major pipeline stages, described as follows:
• The fetch pipeline stage primarily involves retrieving instructions from the memory system
• The dispatch pipeline stage is responsible for decoding the instructions supplied by the
• During the execute pipeline stage each execution unit that has an executable instruction
and determining the location of the next instruction retrieval. Additionally, the BPU decodes
branches during the fetch stage and folds out branch instructions before the dispatch stage if
possible.
instruction retrieval stage, and determining which of the instructions are eligible to be
dispatched in the current cycle. In addition, the source operands of the instructions are read
from the appropriate register file and dispatched with the instruction to the execute pipeline
stage. At the end of the dispatch pipeline stage, the dispatched instructions and their
operands are latched by the appropriate execution unit.
executes the selected instruction (perhaps over multiple cycles), writes the instruction’s result
into the appropriate rename register, and notifies the completion stage when the instruction
has finished execution. In the case of an internal exception, the execution unit reports the
exception to the completion/writeback pipeline stage and discontinues instruction execution
until the exception is handled. The exception is not signaled until that instruction is the next to
be completed. Execution of most floating-point instructions is pipelined within the FPU
allowing up to three instructions to be executing in the FPU concurrently. The pipeline stages
for the floating-point unit are multiply, add, and round-convert. Execution of most load/store
instructions is also pipelined. The load/store unit has two pipeline stages. The first stage is for
effective address calculation and MMU translation and the second stage is for accessing the
data in the cache.
5410B–HIREL–09/05