CS42448-CQZ Cirrus Logic Inc, CS42448-CQZ Datasheet - Page 24

• Manufacturer Part Number: CS42448-CQZ
• Description: IC CODEC 108DB 192KHZ 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42448-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 6 ADC/8 DAC
• Thd Plus Noise: - 98 dB ADC / - 98 dB DAC, - 95 dB ADC / - 95 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1151 - BOARD EVAL FOR CS42448 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1033

24
4. APPLICATIONS
4.1
4.2
4.2.1
Overview
The CS42448 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital con-
verters (ADC) implemented using multi-bit delta-sigma techniques and 8 digital-to-analog converters (DAC)
also implemented using multi-bit delta-sigma techniques.
Other functions integrated within the CODEC include independent digital volume controls for each DAC, dig-
ital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC high-pass
filters, an on-chip voltage reference, and Popguard technology that minimizes the effects of output tran-
sients on power-up and power-down.
All serial data is transmitted through two independent serial ports: the DAC serial port and the ADC serial
port. Each serial port can be configured independently to operate at different sample and clock rates, but
both must run synchronous to each other.
The serial audio interface ports allow up to 8 DAC channels and 8 ADC channels in a Time-Division Multi-
plexed (TDM) interface format. In the One-Line Mode (OLM) interface format, the CS42448 will allow up to
6 ADC channels on one data line and up to 8 DAC channels on 2 data lines.
The CS42448 features an Auxiliary Port used to accommodate an additional two channels of PCM data on
the ADC_SDOUT data line in the TDM digital interface format. See
The CS42448 operates in one of three oversampling modes based on the input sample rate. When operat-
ing the CODEC as a slave, mode selection is determined automatically based on the MCLK frequency set-
ting. When operating as a master, mode selection is determined by the ADC and DAC FM bits in register
“Functional Mode (Address 03h)” on page
to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode (DSM) supports input sample rates up
to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode (QSM) supports input sample rates
up to 200 kHz and uses an oversampling ratio of 32x (Note: QSM for the ADC is only supported in the I²S,
Left-Justified, Right-Justified interface formats. QSM for the DAC is supported in the I²S, Left-Justified,
Right-Justified and Time Division Multiplexed interface formats).
All functions can be configured through software via a serial control port operable in SPI Mode or in I²C
Mode.
Figure 2 on page 16
page 41
Analog Inputs
for details.
Line-Level Inputs
AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2.
Figure 10 on page 25
ended signals on all inputs, AIN1-AIN
filters.
For single-ended operation on ADC1-ADC
Control & DAC De-Emphasis (Address 05h)” on page 45
page 53
for the default register settings and options.
for required external components).
shows the recommended connections for the CS42448. See
shows the full-scale analog input levels. The CS42448 also accommodates single-
6
. See
43. Single-Speed Mode (SSM) supports input sample rates up
3
(AIN1 to AIN
“ADC Input Filter” on page 53
6
), the ADCx_SINGLE bit in the register
must be set appropriately (see
for the recommended input
“Register Description” on
CS42448
Figure 27 on
DS648F3
“ADC