MAX9856ETL+ Maxim Integrated Products, MAX9856ETL+ Datasheet - Page 37

• Manufacturer Part Number: MAX9856ETL+
• Description: IC CODEC AUDIO LP 40TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Audio Codecr

Specifications of MAX9856ETL+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 77 / 91
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 91
• Voltage - Supply, Analog: 1.71 V ~ 3.6 V
• Voltage - Supply, Digital: 1.71 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN Exposed Pad
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Interface Type: I2C
• Resolution: 18 bit
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 2.9 mA
• Thd Plus Noise: 82 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 2
• No. Of Output Channels: 2
• Adc / Dac Resolution: 18bit
• Adcs / Dacs Signal To Noise Ratio: 91dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX9856 features headset detection that can detect
the insertion and removal of a jack as well as the load
type. When a jack is detected, an interrupt on IRQ can be
triggered to alert the microcontroller of the event. Figure 6
shows the typical configuration for jack detection and
Table 14 shows the headset detect control register and
bit description.
When the MAX9856 is in shutdown and the power sup-
ply is available, sleep mode jack detection can be
enabled to detect jack insertion. Sleep mode applies a
2µA pullup current to JACKSNS and HPL, which forces
the voltage on JACKSNS and HPL to AVDD when no
load is applied. When a jack is inserted, either JACK-
SNS, HPL, or both are loaded sufficiently to reduce the
output voltage to nearly 0V and clear the JKSNS or
LSNS bits, respectively. The change in the LSNS and
JKSNS bits sets JDET and triggers an interrupt on IRQ
if IJDET is set. The interrupt signals the microcontroller
that a jack has been inserted, allowing the microcon-
troller to respond as desired.
When the MAX9856 is in normal operation and the
microphone interface is enabled, jack insertion and
Figure 6. Example Jack Configuration for Jack Detection
Figure 7. Current on HPL, HPR, or JACKSNS During Impedance Detection
2mA
I
SET EN BITS TO 1
______________________________________________________________________________________
t
O
Powered-On Jack Detection
Sleep-Mode Jack Detection
Headset Detection
DirectDrive Headphone Amplifiers
GND
READ HSDETL,
HSDETR,
t
O
JSDET
+ 24ms
MIC
Low-Power Audio CODEC with
HPR
HPL
removal can be detected through the JACKSNS pin. As
shown in Figure 6, V
When a microphone is connected, V
be between 0V and 95% of V
removed, V
es JKMIC to be set, alerting the system that the head-
set has been removed. Alternatively, if the jack is
inserted, V
and JKMIC is cleared, alerting that a jack has been
inserted. The JKMIC bit can be configured to create a
hardware interrupt that alerts the microcontroller of jack
removal and insertion events.
The MAX9856 is able to detect the type of load con-
nected by applying a 2mA pullup current to HPL, HPR,
and JACKSNS. To minimize click-and-pop the current
is ramped up and down over a 24ms period. The 2mA
current can be individually applied to HPL, HPR, and
JACKSNS by appropriately configuring the EN bits.
When the 2mA current has finished ramping, HSDETL,
HSDETR, and JSDET are updated to reflect the mea-
sured impedance. EN must be cleared and reset to re-
measure the impedance. Figure 7 and Table 15
illustrate the impedance detection process.
HPL
HPR
SET EN BITS TO 0
t
f
MIC
MIC
- 24ms
increases to V
decreases to below 95% of V
MICBIAS
JACKSNS
MIC
is pulled up by MICBIAS.
IMPEDANCE
DETECTION
COMPLETE
MICBIAS
MICL
MICBIAS
t
f
Impedance Detection
MIC
. This event caus-
. If the jack is
is assumed to
MICBIAS
37