CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 28

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

28
4. APPLICATIONS
4.1
4.1.1
System Clocking
The CS42324 will operate at sampling frequencies from 4 kHz to 108 kHz. This range is divided into two
speed modes as shown in
The CS42324 has two serial ports which can operate synchronously or asynchronously. Serial Port 1
(SP1) consists of the SCLK1 and LRCK1 signals. Serial Port 2 (SP2) consists of the SCLK2 and LRCK2
signals. The serial audio output, SDOUT, and serial audio inputs, SDIN1 and SDIN2, can be independent-
ly assigned to either of the two serial ports for ease of clocking. Each serial port may be independently
placed into Single- or Double-Speed Mode. The serial ports may also be independently placed into Master
or Slave Mode.
Master Clock
In both Synchronous and Asynchronous Modes, MCLKx (MCLK1 and/or MCLK2) and the corresponding
LRCKx must maintain an integer ratio. Some common ratios are shown in
frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out
of the device. The SP1_SPEED and SP2_SPEED bits and the MCLKx FREQ bits configure the device to
generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode when auto detect
mode is disabled.
and LRCKx frequencies.
MCLKx FREQ [1:0]
MCLKx FREQ [1:0]
DOUBLE SPEED
SINGLE SPEED
MODE (DSM)
MODE (SSM)
MDIV pin
MDIV pin
Mode
Mode
Single-Speed
Double-Speed
Speed Mode
Tables 3
Table 4. Double-Speed Mode Common Clock Frequencies
Table 3. Single-Speed Mode Common Clock Frequencies
LRCKx
LRCKx
(kHz)
(kHz)
88.2
44.1
Table
64
96
32
48
and
2.
4
11.2896
12.2880
illustrate several standard audio sample rates and the required MCLKx
8.1920
Master Mode Sampling
128x
Table 2. Speed Modes
128x
00
0
-
-
-
-
-
50-108 kHz
Frequency
4-54 kHz
12.2880
16.9344
18.4320
192x
192x
01
-
-
-
-
-
-
16.3840
22.5792
24.5760
12.2880
11.2896
8.1920
256x
256x
Sampling Frequency
10
00
1
MCLKx (MHz)
0
MCLKx (MHz)
50-108 kHz
Slave Mode
4-54 kHz
12.2880
16.9344
18.4320
24.5760
33.8680
36.8640
384x
384x
01
11
-
-
Tables 3
16.3840
22.5792
24.5760
512x
512x
10
and 4. The LRCKx
1
-
-
-
-
-
CS42324
24.5760
33.8680
36.8640
DS721A6
768x
768x
11
-
-
-
-
-
-