CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 53

IC CODEC STEREO AUDIO 48LQFP

CS42324-CQZ

Manufacturer Part Number
CS42324-CQZ
Description
IC CODEC STEREO AUDIO 48LQFP
Manufacturer
Cirrus Logic Inc
Type
Audio Codecr
Datasheet

Specifications of CS42324-CQZ

Package / Case
48-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
1 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
95 / 100
Voltage - Supply, Analog
3.13 V ~ 3.47 V
Voltage - Supply, Digital
3.13 V ~ 3.47 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Adc Inputs
1
Number Of Dac Outputs
2
Conversion Rate
96 KSPS
Interface Type
Serial (I2S, SPI)
Resolution
24 bit
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Number Of Channels
1 ADC/2 DAC
Supply Current
10 mA to 24 mA
Thd Plus Noise
- 88 dB ADC / - 90 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1498 - BOARD EVAL FOR CS42324 CODEC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1602

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS42324-CQZ
Manufacturer:
TI
Quantity:
2 435
Part Number:
CS42324-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS721A6
6.9.3
6.10
6.10.1 DAC1 De-Emphasis Control
6.10.2 DAC1 Single Volume Control
6.10.3 DAC1 Soft Ramp Control
DAC1_DEPH
7
DAC1 Control (Address 0Bh)
Analog Input Selection
These bits are used to select the input source for the ADC.
This bit enables the digital filter to apply the standard 15
sample rate (Fs) of 44.1 kHz. De-emphasis is available only in Single-Speed Mode.
The individual channel volume levels are independently controlled by their respective Volume Control reg-
isters when this function is disabled. When enabled, the volume on DAC1 channels is determined by the
DAC1A Volume Control register and the DAC1B Volume Control register is ignored.
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
0
1
000
001
010
011
100
101
110
111
0
1
0
1
0
1
AIN_SEL[2:0]
DAC1_DEPH
DAC1_SNGVOL
DAC1_SOFT
ADC_SOFT
DAC1_SNGV
OL
6
Off
On
Reserved
Line-Level Input Pair 1
Line-Level Input Pair 2
Line-Level Input Pair 3
Line-Level Input Pair 4
Line-Level Input Pair 5
Reserved
Reserved
Off
On (valid for Fs = 44.1 kHz)
Off
On
DAC1_SOFT
Off
On
5
DAC1_ZC
4
DAC1 De-Emphasis Control
DAC1 Single Volume Control
DAC1 Soft Ramp Control
ADC Soft Ramp Control
ADC Soft Ramp Control
LOOPBACK
DAC1_
3
μ
s/50
μ
s digital de-emphasis filter response for a
DAC1_INV
2
DAC1_MIX1
1
CS42324
DAC1_MIX0
0
53

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