CS4205-KQZ Cirrus Logic Inc, CS4205-KQZ Datasheet - Page 58

• Manufacturer Part Number: CS4205-KQZ
• Description: IC CODEC AC97 I2S 48-LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codec '97r

Specifications of CS4205-KQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 18, 20 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPs
• Interface Type: Serial (5-Wire)
• Resolution: 18 bit, 20 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Channels: 1 ADC, 1 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1182

8. SONY/PHILIPS DIGITAL
The S/PDIF digital output is used to interface the
CS4205 to consumer audio equipment external to
the PC. This output provides an interface for stor-
ing digital audio data or playing digital audio data
to digital speakers. Figure 22 illustrates the circuits
necessary for implementing the IEC-958 optical or
consumer interface. For further information on
S/PDIF operation see application note AN22: Over-
view of Digital Audio Interface Data Structures [3].
For further information on S/PDIF recommended
transformers see application note AN134: AES and
S/PDIF Recommended Transformers [4].
9. EXCLUSIVE FUNCTIONS
Some of the digital pins on the CS4205 have mul-
tiplexed functionality. These functions are mutual-
ly exclusive and cannot be requested at the same
time. The following pairs of functions are mutually
exclusive:
•
58
SPDO/SDO2
DVdd
INTERFACE (S/PDIF)
GPIO and Serial Data Port (GPIO0 pin is
shared with LRCLK pin, GPIO1 pin is shared
with SDOUT pin, and GPIO[4:2] pins are
shared with SDI[3:1] pins)
R
R
1
2
247.5 Ω
107.6 Ω
3.3V
S/PDIF_OUT
93.75 Ω
375 Ω
5V
R
1
DGND
R
2
Figure 22. S/PDIF Output
T
1
J1
•
•
Use of the GPIO0/LRCLK, GPIO1/SDOUT, and
GPIO[4:2]/SDI[3:1] pins for serial data port has
priority over their GPIO functionality. There is no
priority assigned to the other two exclusive func-
tions. A function currently in use must be disabled
or powered down before the corresponding exclu-
sive function can be enabled. The following control
bits for these functions will behave differently than
normal bits: the EAPD bit in the Powerdown Con-
trol/Status Register (Index 26h), the GC[4:0] bits in
the GPIO Pin Configuration Register (Index 4Ch),
the SPEN bit in the S/PDIF Control Register (Index
68h), and the SDI[3:1], SDO2, and SDSC bits in
the Serial Port Control Register (Index 6Ah). These
bits can become read-only bits if they control a fea-
ture that is currently unavailable because the corre-
sponding exclusive feature is already in use, or the
corresponding master control for this feature is not
set.
EAPD and Serial Data Port Serial Clock
(EAPD pin is shared with SCLK pin)
S/PDIF and Second Serial Data Port (SPDO pin
is shared with SDO2 pin)
0.1 µ F
+5V_PCI
DGND
SPDO/SDO2
8.2 kΩ
4
3
2
1
TOTX-173
CS4205
5
6
DS489PP4
DGND
DGND