AD1838AAS-REEL Analog Devices Inc, AD1838AAS-REEL Datasheet
AD1838AAS-REEL
Specifications of AD1838AAS-REEL
Related parts for AD1838AAS-REEL
AD1838AAS-REEL Summary of contents
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FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports kHz Sample Rates 192 kHz Sample Rate Available on 1 DAC Supports 16-, 20-, 24-Bit Word Lengths Multibit - Modulators with Perfect Differential ...
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AD1838A TEST CONDITIONS Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock DAC Input Signal ADC Input Signal Input Sample Rate ( Measurement Bandwidth Word Width Load Capacitance Load Impedance Performance of all channels is identical (except for ...
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Parameter ADC DECIMATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 96 kHz* Pass Band Pass-Band Ripple ...
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AD1838A TIMING SPECIFICATIONS Parameter MASTER CLOCK AND RESET t MCLK High MH t MCLK Low ML PD/RST Low t PDR SPI PORT t CCLK High CCH t CCLK Low CCL t CCLK Period CCP t CDATA Setup CDS t CDATA ...
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Parameter TDM256 MODE (Master, 48 kHz and 96 kHz) t BCLK Delay TBD t FSTDM Delay FSD t ASDATA Delay TABDD t DSDATA1 Setup TDDS t DSDATA1 Hold TDDH TDM256 MODE (Slave, 48 kHz and 96 kHz) f BCLK Frequency ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Model AD1838AAS AD1838AAS-REEL AD1838AASZ* AD1838AASZ-REEL* –40°C to +85°C EVAL-AD1838AEB *Z = Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device ...
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DVDD CLATCH CIN PD/RST AGND OUTLN1 OUTLP1 OUTRN1 OUTRP1 AGND AVDD OUTLN2 OUTLP2 Pin No. Mnemonic 1, 39 DVDD 2 CLATCH 3 CIN PD/RST 4 5, 10, 16, 24, 30, 34 AGND 6, 12, 25 OUTLNx 7, 13, 26 OUTLPx ...
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AD1838A–Typical Performance Characteristics 0 –50 –100 –150 FREQUENCY – Normalized to TPC 1. ADC Composite Filter Response 5 0 –5 –10 –15 –20 –25 – FREQUENCY – Hz TPC 2. ADC High-Pass Filter Response, ...
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FREQUENCY – kHz TPC 7. DAC Composite Filter Response, f 0.10 0.05 0 –0.05 –0. FREQUENCY – kHz TPC 8. DAC Composite Filter Response, f (Pass-Band Section) REV. A 0.2 ...
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AD1838A TERMINOLOGY Dynamic Range The ratio of a full-scale input signal to the integrated input noise in the pass band ( kHz), expressed in decibels. Dynamic range is measured with a –60 dB input signal and is ...
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FUNCTIONAL OVERVIEW ADCs There are two ADC channels in the AD1838A, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate kHz. The ADCs include on-board ...
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AD1838A DAC INPUT CLOCK SCALING 1 MCLK 2 12.288MHz 2/3 ADC OUTPUT t CLS t CLATCH CCP CCLK CIN D15 D14 t COUT COE RESET and Power-Down PD/RST powers down the chip and sets the control registers to their default ...
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The DAC serial data input mode defaults to I Bits 5, 6, and 7 in DAC Control Register 1, the mode can be changed to RJ, DSP, LJ, or Packed Mode 256. The word width defaults to 24 bits but ...
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AD1838A t ABH ABCLK t ABL t ALS ALRCLK ASDATA LEFT-JUSTIFIED MSB MODE ASDATA COMPATIBLE MODE ASDATA RIGHT-JUSTIFIED MODE t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATA LEFT-JUSTIFIED MSB MODE t DDH DSDATA 2 ...
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LRCLK BCLK ADC DATA LRCLK BCLK ADC DATA LRCLK BCLK DAC DATA LRCLK BCLK DAC DATA REV. A 128 BCLKs 16 BCLKs SLOT 1 SLOT 5 SLOT 2 SLOT 3 SLOT 4 SLOT 6 LEFT RIGHT MSB MSB – 1 ...
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AD1838A t ABH ABCLK t ABL t ALS ALRCLK t ALH ASDATA MSB Figure 9. ADC Packed Mode Timing DBCLK DLRCLK t ABDD DSDATA MSB – 1 –16– t DBH t DBL t DLS t DLH t DDS MSB MSB ...
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Pin Name ASDATA (O) DSDATA1 (I) DSDATA2 (I)/AAUXDATA1 (I) DSDATA3 (I)/AAUXDATA2 (I) AAUXDATA3 (I) ALRCLK (O) ABCLK (O) DLRCLK (I)/AUXLRCLK (I/O) DBCLK (I)/AUXBCLK (I/O) DAUXDATA (O) FSTDM BCLK TDM MSB TDM 1ST ASDATA1 CH TDM (OUT) INTERNAL ASDATA ADC L1 ...
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AD1838A LRCLK BCLK ADC NO. 1 SLAVE DATA MCLK LRCLK BCLK ADC NO. 2 SLAVE DATA MCLK LRCLK BCLK ADC NO. 3 SLAVE DATA MCLK Figure 12. Auxiliary Mode Connection (Master Mode) to SHARC LRCLK BCLK ADC NO. 1 MASTER ...
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CONTROL/STATUS REGISTERS The AD1838A has 13 control registers which are used to set the operating mode of the part. The other two registers, ADC Peak 0 and ADC Peak 1, are read-only and should not be programmed. Each ...
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AD1838A Register Address Register Name 0000 DACCTRL1 0001 DACCTRL2 0010 DACVOL1 0011 DACVOL2 0100 DACVOL3 0101 DACVOL4 0110 DACVOL5 0111 DACVOL6 1000 Reserved 1001 Reserved 1010 ADCPeak0 1011 ADCPeak1 1100 ADCCTRL1 1101 ADCCTRL2 1110 ADCCTRL3 1111 Reserved Address R/W RES ...
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Table VIII. DAC Volume Control Address R/W RES DAC Volume 15, 14, 13 0010 = DACL1 0 0 0000000000 = Mute 0011 = DACR1 0000000001 = 1/1023 ...
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AD1838A CASCADE MODE Dual AD1838A Cascade The AD1838A can be cascaded to an additional AD1838A, which, in addition to six external stereo ADCs and one external stereo DAC, can be used to create a 32-channel audio system with 16 inputs ...
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F 600Z 5.76k 5.76k + AUDIO INPUT 120pF NPO 100pF NPO 237 OP275 V REF 5.76k 5.76k 750k 237 OP275 V REF Figure 16. Typical ADC Input Filter Circuit REV. A OUTNx 11k ADCxN 1nF NPO 100pF NPO OUTPx ...
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AD1838A 10 6 2.20 2 2.00 1.80 0.25 MAX Revision History Location 2/04—Data Sheet changed from REV REV. A. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . ...