AD1838AAS-REEL Analog Devices Inc, AD1838AAS-REEL Datasheet - Page 22

• Manufacturer Part Number: AD1838AAS-REEL
• Description: IC CODEC 2ADC/6DAC 24 BIT 52MQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1838AAS-REEL

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 105 / 108
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-BQFP

AD1838A
CASCADE MODE
Dual AD1838A Cascade
The AD1838A can be cascaded to an additional AD1838A,
which, in addition to six external stereo ADCs and one external
stereo DAC, can be used to create a 32-channel audio system
with 16 inputs and 16 outputs. The cascade is designed to
connect to a SHARC DSP and operates in a time division
multiplexing (TDM) format. Figure 14 shows the connection
diagram for cascade operation. The digital interface for both
parts must be set to operate in Auxiliary 512 mode by program-
ming ADC Control Register 2. AD1838A No. 1 is set as a master
device by connecting the M/S pin to DGND and AD1838A
No. 2 is set as a slave device by connecting the M/S to ODVDD.
Both devices should be run from the same MCLK and PD/RST
signals to ensure that they are synchronized.
(SLAVE)
SHARC
RCLKx
TCLKx
RFSx
DRx
DTx
BCLK
AUX ADC
DTx
DRx
(SLAVE)
RFSx
DTx
DRx
ASDATA
ALRCLK
ABCLK
L1
L1
AUX ADC
(SLAVE)
MSB
L2
L2
MSB
AD1838A NO. 1 DACs
Figure 15. Dual AD1838A Cascade Timing
AD1838A NO. 1 ADCs
L3
L3
MSB – 1
MSB – 1
256 BCLKs
AD1838A NO. 1
Figure 14. Dual AD1838A Cascade
L4
L4
(MASTER)
DAUXDATA
AUX ADC
(SLAVE)
DSDATA
R1
R1
32 ABCLKs
R2
R2
LSB
LSB
R3
R3
AUX DAC
(SLAVE)
–22–
R4
R4
DON’ T CARE
With Device 1 set as a master, it will generate the frame-sync
and bit clock signals. These signals are sent to the SHARC and
Device 2 ensuring that both know when to send and receive data.
The cascade can be thought of as two 256-bit shift registers, one
for each device. At the beginning of a sample interval, the shift
registers contain the ADC results from the previous sample
interval. The first shift register (Device 1) clocks data into the
SHARC and also clocks in data from the second shift register
(Device 2). While this is happening, the SHARC is sending
DAC data to the second shift register. By the end of the sample
interval, all 512 bits of ADC data in the shift registers will have
been clocked into the SHARC and been replaced by DAC data,
which is subsequently written to the DACs. Figure 15 shows the
timing diagram for the cascade operation.
L1
L1
L2
L2
AUX ADC
(SLAVE)
AD1838A NO. 2 DACs
AD1838A NO. 2 ADCs
L3
L3
256 BCLKs
L4
ASDATA
ALRCLK
ABCLK
L4
R1
R1
AUX ADC
(SLAVE)
R2
R2
R3
R3
AD1838A NO. 2
DAUXDATA
(SLAVE)
AUX ADC
R4
R4
(SLAVE)
DSDATA
AUX DAC
(SLAVE)
REV. A