LTC4266IUHF#PBF Linear Technology, LTC4266IUHF#PBF Datasheet

Page 1

FeAtures Four Independent PSE Channels n Compliant with IEEE 802.3at Type 1 and 2 n 0.34Ω Total Channel Resistance n 130mW/Port at 600mA Advanced Power Management n 8-Bit Programmable Current Limit (I 7-Bit Programmable Overload Currents (I Fast Shutdown of Preselected Ports 14.5-Bit Port Current/Voltage Monitoring 2-Event Classification Very High Reliability 4-Point PD Detection: n 2-Point Forced Voltage 2-Point Forced Current High Capacitance Legacy Device Detection n LTC4259A-1 and LTC4258 Pin and SW Compatible n 2 1MHz I C Compatible Serial Control Interface n Midspan Backoff Timer n Supports Proprietary Power Levels Above 25W n Available in 38-Pin 5mm × 7mm QFN and 36-Pin n SSOP Packages ApplicAtions High Power PSE Switches/Routers n ...

Page 2

... JA orDer inForMAtion LEAD FREE FINISH TAPE AND REEL LTC4266CGW#PBF LTC4266CGW#TRPBF LTC4266IGW#PBF LTC4266IGW#TRPBF LTC4266CUHF#PBF LTC4266CUHF#TRPBF LTC4266IUHF#PBF LTC4266IUHF#TRPBF Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  Operating Temperature Range LTC4266C ................................................ 0°C to 70°C LTC4266I .............................................–40°C to 85°C Junction Temperature (Note 2) ............................. 125°C Storage Temperature Range .................. – ...

Page 3

SYMBOL PARAMETER –48V Supply Voltage Undervoltage Lock-out Level V V Supply Voltage DD DD Undervoltage Lock-out Allowable Digital Ground Offset I V Supply Current Supply Current DD DD Detection Detection Current – Force Current Detection Voltage – Force Voltage Detection Current Compliance V Detection Voltage Compliance OC Detection Voltage Slew Rate Min. Valid Signature Resistance Max. Valid Signature Resistance Classification V Classification Voltage CLASS ...

Page 4

LTC4266 electricAl chArActeristics temperature range, otherwise specifications are at T noted. (Notes 3, 4) SYMBOL PARAMETER Current Sense V Overcurrent Sense Voltage CUT Overcurrent Sense in Auto Mode V Active Current Limit in 802.3af Compliant LIM Mode V Active Current Limit in High Power Mode LIM V Active Current Limit in Auto Mode LIM V DC Disconnect Sense Voltage MIN V Short-Circuit Sense SC Port Current ReadBack Resolution LSB Weight 50-60Hz Noise Rejection Port Voltage ReadBack Resolution LSB Weight 50-60Hz noise rejection Digital Interface V Digital Input Low Voltage ...

Page 5

SYMBOL PARAMETER Timing Characteristics t Detection Time DET t Detection Delay DETDLY t First Class Event Duration CLE1 t First Mark Event Duration ME1 t Second Class Event Duration CLE2 t Second Mark Event Duration ME2 t Third Class Event Duration CLE3 t Power On Delay in Auto Mode PON Turn On Rise Time Turn On Ramp Rate Fault Delay Midspan Mode Detection Backoff Power Removal Detection Delay t Maximum Current Limit Duration During Port START ...

Page 6

LTC4266 electricAl chArActeristics temperature range, otherwise specifications are at T noted. (Notes 3, 4) SYMBOL PARAMETER Timing Clock Frequency t Bus Free Time 1 t Start Hold Time 2 t SCL Low Time 3 t SCL High Time 4 t Data Hold Time 5 t Data Set-Up Time 6 t Start Set-Up Time 7 t Stop Set-Up Time 8 t SCL, SDAIN Rise Time r t ...

Page 7

Power On Sequence in Auto Mode 10 FORCED CURRENT DETECTION 0 GND –10 FORCED VOLTAGE –20 DETECTION –30 802.3af PORT 1 CLASSIFICATION V = 3.3V DD – –54V EE POWER ON – –60 –70 100ms/DIV 4266 G01 2-Event Classification in ...

Page 8

LTC4266 typicAl perForMAnce chArActeristics 802.3af I Threshold vs LIM Temperature 108. 3. –54V 0.25 SENSE REG 48h = 80h 107.25 PORT 1 106.50 105.75 105.00 – TEMPERATURE (°C) 802.3af I Threshold vs CUT Temperature ...

Page 9

ADC Noise Histogram Current Readback in Slow Mode 300 V – 110.4mV SENSEn EE 250 200 150 100 50 0 6139 6141 6143 6145 6147 ADC OUTPUT 4266 G17 ADC Integral Nonlinearity Voltage Readback in Fast Mode 1.0 0.5 0 –0.5 –1 ...

Page 10

LTC4266 test tiMing DiAgrAMs V PORTn V INT Figure 1. Detect, Class and Turn-On Timing in Auto or Semiauto Modes V LIM V CUT SENSEn EE 0V INT Figure 2. Current Limit Timing V GATEn t MSD t SHDN MSD or SHDNn 4266 F04 Figure 4. Shut Down Delay Timing 0 t CLASSIFICATION DET FORCED-CURRENT FORCED- t ...

Page 11

DiAgrAMs SCL SDA AD3 AD2 AD1 AD0 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA AD3 AD2 AD1 AD0 R/W ACK START BY ACK BY MASTER ...

Page 12

LTC4266 tiMing DiAgrAMs SCL SDA 0 START BY MASTER SCL SDA 0 START BY MASTER  1 AD3 AD2 AD1 AD0 R/W ACK ACK BY SLAVE FRAME 1 FRAME 2 SERIAL ...

Page 13

Functions RESET: Chip Reset, Active Low. When the RESET pin is low, the LTC4266 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4266 begins normal opera- tion. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1µs wide from resetting the LTC4266. Internally pulled MID: Midspan Mode Input. When high, the LTC4266 acts as a midspan device. Internally pulled down to D INT: Interrupt Output, Open Drain. INT will pull low when any one of several events occur in the LTC4266. It will return to a high impedance state when bits are set in the Reset PB register (1Ah). The INT signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. Individual INT events can be disabled using the Int Mask register (01h). See Register Functions and Applications Information for more information. The INT pin is only updated between transactions. SCL: Serial Clock Input. High impedance clock input for 2 the I C serial interface bus. SCL must be tied high if not used. SDAOUT: Serial Data Output, Open Drain Data Output for ...

Page 14

LTC4266 pin Functions GATE4: Port 4 Gate Drive. GATE4 should be connected to the gate of the external MOSFET for port 4. When the MOSFET is turned on, the gate voltage is driven to 13V (typ) above V . During a current limit condition, the EE voltage at GATE4 will be reduced to maintain constant current through the external MOSFET. If the fault timer expires, GATE4 is pulled down, turning the MOSFET off and recording event. If the port is unused, CUT START float the GATE4 pin. OUT4: Port 4 Output Voltage Monitor. OUT4 should be connected to the output port. ...

Page 15

Overview Power over Ethernet, or PoE standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE spec, known as 802.3af, allowed for 48V DC power 13W. This initial spec was widely popular, but 13W was not adequate for some requirements. In 2009, the IEEE released a new standard, known as 802.3at or PoE+, increasing the voltage and current requirements to provide 25W of power. The IEEE standard also defines PoE terminology. A device that provides power to the network is known as a PSE, or power sourcing equipment, while a device that draws power from the network is known as a PD, or powered device. PSEs come in two types: Endpoints (typically network switches or routers), which provide data and power; and ...

Page 16

LTC4266 operAtion more power that the PSE has available. The classification step is optional PSE chooses not to classify a PD, it must assume that the 13W (full 802.3af power) device. New in 802.3at The newer 802.3at standard supersedes 802.3af and brings several new features: • may draw as much as 25.5W. Such PDs (and the PSEs that support them) are known as Type 2. Older 13W 802.3af equipment is classified as Type 1. Type 1 PDs will work with all PSEs; Type 2 PDs may require Type 2 PSEs to work properly. The LTC4266 is designed to work in both Type 1 and Type 2 PSE designs, and also supports non-standard configurations at higher power levels. • The Classification protocol is expanded to allow Type 2 PSEs to detect Type 2 PDs, and to allow Type 2 PDs to determine if they are connected to a Type 2 PSE. Two versions of the new Classification protocol are avail- able: an expanded version of the 802.3af Class Pulse protocol, and an alternate method integrated with the existing LLDP protocol (using the Ethernet data path). The LTC4266 fully supports the new Class Pulse protocol and is also compatible with the LLDP protocol (which is implemented in the data communications layer, not in the PoE circuitry). • Fault protection current levels and timing are adjusted to reduce peak power in the MOSFET during a fault; this allows the new 25.5W power levels to be reached using the same MOSFETs as older 13W designs. ...

Page 17

ApplicAtions inForMAtion Operating Modes The LTC4266 includes four independent ports, each of which can operate in one of four modes: Manual, Semi- auto, Auto, or Shutdown. • In manual mode, the port waits for instructions from the host system before taking any action. It runs a single detection or classification cycle when commanded to by the host, and reports the result in its Port Status register. The host system can command the port to turn on or off the power at any time. • In semi-auto mode, the port repeatedly attempts to detect and classify any PD attached to it. It reports the status of these attempts back to the host, and waits for a command from the host before turning on power to ...

Page 18

LTC4266 ApplicAtions inForMAtion 4-Point Detection The LTC4266 uses a 4-point detection method to discover PDs. False-positive detections are minimized by check- ing for signature resistance with both forced-current and forced-voltage measurements. Initially, two test currents are forced onto the port (via the OUTn pin) and the resulting voltages are measured. The detection circuitry subtracts the two V-I points to determine the resistive slope while removing offset caused by series diodes or leakage at the port (see Figure 12). If the forced-current detection yields a valid signature resistance, two test voltages are then forced onto the port and the resulting currents are measured and subtracted. Both methods must report valid resistances for the port to report a valid detection. PD signature resistances between 17k and 29k (typically) are detected as valid and reported as Detect Good in the corresponding Port Status register. Values outside this ...

Page 19

ApplicAtions inForMAtion capacitance (>10μF) as the detection signature. Note that PDs in this range of capacitance are defined as invalid PSE that detects legacy PDs is technically noncompliant with the IEEE spec. The LTC4266 can be configured to detect this type of legacy PD. Legacy detection is disabled by default, but can be manually enabled on a per-port basis. When enabled, the port will report detect good when it sees either a valid IEEE high-capacitance legacy PD. With legacy mode disabled, only valid IEEE PDs will be recognized. CLASSIFICATION 802.3af Classification A PD can optionally present a classification signature to the PSE to indicate the maximum power it will draw while operating. The IEEE specification defines this signature as a constant current draw when the PSE port voltage is in the V range (between 15.5V and 20.5V), with the current CLASS level indicating one of 5 possible PD classes. Figure 14 shows a typical PD load line, starting with the slope of the 25kΩ signature resistor below 10V, then transitioning to the classification signature current (in this case, Class 3) in the V range. Table 3 shows the possible clas- CLASS sification values. Table 3. Classification Values CLASS RESULT Class 0 No Class Signature Present; Treat Like Class 3 Class 1 3W Class 2 7W Class 3 13W ...

Page 20

LTC4266 ApplicAtions inForMAtion power status register to indicate that it ran the second classification cycle. The second cycle alerts the PD that it is connected to a Type 2 PSE which can supply Type 2 power levels. 2-event ping-pong classification is enabled by setting a bit in the port’s high power mode register. Note that a ping- pong enabled port only runs the second classification cycle when it detects a Class 4 device; if the first cycle returns Class the port assumes it is connected to a Type 1 PD and does not run the second classification cycle. Invalid Type 2 Class Combinations The 802.3at spec defines a Type 2 PD class signature as two consecutive Class 4 results; a Class 4 followed by a Class 0-3 is not a valid signature. In auto mode, the LTC4266 will power a detected PD regardless of the clas- sification results, with one exception: if the PD presents an invalid Type 2 signature (Class 4 followed by Class 0 to 3), the LTC4266 will not provide power and will restart the detection process. To aid in diagnosis, the port status register will always report the results of the last class pulse invalid Class 4–Class 2 combination would report a second class pulse was run in the High Power Status register (which implies that the first cycle found Class 4), and Class 2 in the port status register. POWER CONTROL External MOSFET, Sense R Summary The primary function of the LTC4266 is to control the delivery of power to the PSE port. It does this by control- ...

Page 21

ApplicAtions inForMAtion Per the IEEE specification, the LTC4266 will automatically set I to 425mA (shown in bold in Table 4) during inrush LIM at port turn-on, and then switch to the programmed I setting once inrush has completed. To maintain IEEE compliance, I should kept at 425mA for all Type 1 PDs, LIM and 850mA if a Type detected. I reset to 425mA when a port turns off. Table 4. Example Current Limit Settings INTERNAL REGISTER SETTING (hex) I (mA 0.5Ω LIM SENSE 53 88 106 08 159 89 213 80 266 8A 319 ...

Page 22

LTC4266 ApplicAtions inForMAtion MOSFET Fault Detection LTC4266 PSE ports are designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external MOSFET to be damaged. A failed MOSFET may short source to drain, which will make the port ap- pear when it should be off; this condition may also cause the sense resistor to fuse open, turning off the port but causing the LTC4266 SENSE pin to rise to an abnormally high voltage. A failed MOSFET may also short from gate to drain, causing the LTC4266 GATE pin to rise to an abnormally high voltage. The LTC4266 SENSE and GATE pins are designed to tolerate up to 80V faults without damage. If the LTC4266 sees any of these conditions for more than 180μs, it disables all port functionality, reduces the gate drive pull-down current for the port and reports a FET Bad fault. This is typically a permanent fault, but the host can attempt to recover by resetting the port resetting the entire chip if a port reset fails to clear the fault. If the MOSFET is in fact bad, the fault will quickly return, and the port will disable itself again. The remaining ports of the LTC4266 are unaffected. An open or missing MOSFET will not trigger a FET Bad fault if the LTC4266 attempts fault, but will cause a t START to turn on the port. ...

Page 23

ApplicAtions inForMAtion SERIAL DIGITAL INTERFACE Overview The LTC4266 communicates with the host using a standard 2 SMBus/I C 2-wire interface. The LTC4266 is a slave-only device, and communicates with the host master using the standard SMBus protocols. Interrupts are signaled to the host via the INT pin. The Timing Diagrams (Figures 6 through 10) show typical communication waveforms and their timing relationships. More information about the SMBus data protocols can be found at www.smbus.org. The LTC4266 requires both the present for the serial interface to function. Bus Addressing The LTC4266’s primary serial bus address is 010xxxxb, with the lower four bits set by the AD3-AD0 pins; this allows LTC4266s on a single bus. All LTC4266s also respond to the address 0110000b, allowing the host to write the same command (typically configuration commands) ...

Page 24

LTC4266 ApplicAtions inForMAtion + C76 C78 10µF 0.22µF 63V 100V C77 0.22µF 100V R58 R54 10 56k C79 R60 2200pF voltage transient on the V supply and possibly causing EE the LTC4266 to reset due to a UVLO fault. A 1μF , 100V X7R capacitor placed near the minimize spurious resets. Isolating the Serial Bus The LTC4266 includes a split SDA pin (SDAIN and SDAOUT) to ease opto-isolation of the bidirectional SDA line. IEEE 802.3 Ethernet specifications require that network segments (including PoE circuitry) be electrically isolated from the chassis ground of each network interface device. However, network segments are not required to be isolated from each other, provided that the segments are connected to devices residing within a single building on a single ...

Page 25

ApplicAtions inForMAtion V CPU DD U1 SCL SDA TO CONTROLLER SMBALERT GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L 0.1µ 200 2k 200 HCPL-063L U3 200 200 0.1µF HCPL-063L ISOLATED 3.3V + 10µF ISOLATED GND 2 Figure 18. Opto-Isolating the I ...

Page 26

LTC4266 ApplicAtions inForMAtion Output Cap Each port requires a 0.22μF cap across its outputs to keep the LTC4266 stable while in current limit during startup or overload. Common ceramic capacitors often have sig- nificant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. To minimize this problem, X7R ceramic capacitors rated for at least 100V are recommended. ESD/Cable Discharge Protection Ethernet ports can be subject to significant ESD events when long data cables, each potentially charged to thou- sands of volts, are plugged into the low impedance of the RJ45 jack. To protect against damage, each port requires a pair of clamp diodes; one to AGND and one to V 10). An additional surge suppressor is required for each LTC4266 chip from V to AGND. The diodes at the ports EE steer harmful surges into the supply rails, where they are absorbed by the surge suppressor and the V capacitance. The surge suppressor has the additional benefit of protecting the LTC4266 from transients on the V supply. EE S1B diodes work well as port ...

Page 27

ApplicAtions inForMAtion connects to the V plane with a via. Currents from the U1 EE sub-circuit are effectively isolated from the U2 sub-circuit, reducing the layout problem down to 4-port chunks; this arrangement can be expanded for any number of ports. Figure 21 shows an example of good 4-port layout. Each 0.25Ω sense resistor consists of four 1Ω resistors in paral- lel. The four groups of resistors are arranged to minimize the overlap in their current flows, which minimizes mutual resistance. The horizontal slits cut in the copper help to keep the currents separate. Wide copper paths connect each group of resistors to the vias at the center, so the resistance is very low. U1 LTC4266 SENSE1 SENSE2 SENSE3 SENSE4 V EE THIS TRACE PROVIDES BUT ALSO ACTS AS A KELVIN SENSE LINE FOR ...

Page 28

LTC4266 pAckAge Description 36 19 10.804 MIN 1 0.520 ±0.0635 RECOMMENDED SOLDER PAD LAYOUT 7.417 – 7.595** (.292 – .299) 0.254 – 0.406 45° (.010 – .016) 0.231 – 0.3175 0.40 – 1.27 (.0091 – .0125) (.015 – .050) NOTE: ...

Page 29

... NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 5.15 ± ...

Page 30

... S1B Q1 T1 • • 0.01µF 0.01µF 200V 200V 75 75 • • • • 0.01µF 0.01µF 200V 200V 75 75 • • 1000pF 2000V LT 0810 REV A • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 2009 RJ45 CONNECTOR 4266 F22 4266fa ...