LTC4266IUHF#PBF Linear Technology, LTC4266IUHF#PBF Datasheet - Page 26

• Manufacturer Part Number: LTC4266IUHF#PBF
• Description: IC CTRLR IEEE 802.3AT 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC4266IUHF#PBF

• Controller Type: Ethernet Controller (IEEE 802.3)
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-QFN
• Input Voltage: 3.3V
• Supply Current: -2.4mA
• Digital Ic Case Style: QFN
• No. Of Pins: 38
• Uvlo: 25V
• Frequency: 1MHz
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Termination Type: SMD
• Rohs Compliant: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 38
• Mounting: Surface Mount
• Package Type: QFN EP
• Case Length: 7mm
• Screening Level: Industrial
• Filter Terminals: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant

LTC4266
ApplicAtions inForMAtion
Output Cap
Each port requires a 0.22μF cap across its outputs to keep
the LTC4266 stable while in current limit during startup
or overload. Common ceramic capacitors often have sig-
nificant voltage coefficients; this means the capacitance
is reduced as the applied voltage increases. To minimize
this problem, X7R ceramic capacitors rated for at least
100V are recommended.
ESD/Cable Discharge Protection
Ethernet ports can be subject to significant ESD events
when long data cables, each potentially charged to thou-
sands of volts, are plugged into the low impedance of the
RJ45 jack. To protect against damage, each port requires a
pair of clamp diodes; one to AGND and one to V
10). An additional surge suppressor is required for each
LTC4266 chip from V
steer harmful surges into the supply rails, where they are
absorbed by the surge suppressor and the V
capacitance. The surge suppressor has the additional
benefit of protecting the LTC4266 from transients on the
V
S1B diodes work well as port clamp diodes, and an
SMAJ58A or equivalent is recommended for the V
suppressor.
LAYOUT GUIDELINES
Standard power layout guidelines apply to the LTC4266:
place the decoupling caps for the V

EE
supply.
EE
I
CROSSTALK ERROR
1
+ I
to AGND. The diodes at the ports
2
SCALE ERROR
+ I
I
EE
EE
LTC4266
SIGNAL
SENSE
V
GATE
EE
–
V
R
+
V
Figure 19. Layout Affects Current Readback Accuracy
S
S
M
DD
= I
1
and V
R
S1
MUTUAL RESISTANCE
+ I
R
I
1
1
S1
R
M
I
EE
2
+ I
EE
EE
supplies
2
R
EE
bypass
R
(Figure
S2
M
surge
near their respective supply pins, use ground planes, and
use wide traces wherever there are significant currents.
The main layout challenge involves the arrangement of
the current sense resistors, and their connections to
the LTC4266. Because the sense resistor values are very
low, layout parasitics can cause significant errors. Care is
required to achieve specified accuracy, particularly with
disconnect currents.
Figure 19 illustrates the problem. In the example on the
left, two ports have load currents I
the V
R
planes, and vias in the PCB that I
return to the V
age difference between its SENSE and V
the voltage drop across R
R
The example on the right shows how errors can be
minimized with a good layout. The circuit is rearranged
so that R
to the LTC4266 is used as a Kelvin sense trace. V
a perfect Kelvin connection because all four ports con-
trolled by the LTC4266 share the same sense trace, and
because the current through the trace (I
However, as the equation shows, the remaining error is a
small offset term.
Figure 20 shows two LTC4266 chips controlling eight ports
(A though H). The ports are separated into two groups
of four; each has its own trace on the top PCB layer that
M
M
I
represents the combined resistances of any traces,
introduces errors.
SMALL OFFSET ERROR
EE
LTC4266
EE
SENSE
V
GATE
EE
power supply through a mutual resistance R
–
KELVIN SENSE LINE
M
no longer affects V
+
V
R
S
K
SIGNAL
EE
supply. The LTC4266 measures the volt-
V
R
I
S
1
S1
= I
I
2
1
R
S1
R
I
1
– I
S2
S1
+ I
EE
R
, but as the example shows,
2
M
R
+ I
K
4266 F19
S
EE
, and the V
1
1
and I
and I
EE
2
EE
2
share as they
that return to
pins to sense
EE
) is not zero.
connection
EE
is not
4266fa
M
.