CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet - Page 53

• Manufacturer Part Number: CY7C63310-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™IIr

Specifications of CY7C63310-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.5 Interrupt Registers
The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources’ ability to clear posted interrupts.
When an INT_CLRx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. Therefore,
reading these registers gives the user the ability to determine all posted interrupts.
Table 17-1. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]
Table 17-2. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
Table 17-3. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
17.5.1 Interrupt Mask Registers
The Interrupt Mask Registers (INT_MSKx) enable the individual
interrupt sources’ ability to create pending interrupts.
There are four Interrupt Mask Registers (INT_MSK0,
INT_MSK1, INT_MSK2, and INT_MSK3) which may be referred
to in general as INT_MSKx. If cleared, each bit in an INT_MSKx
register prevents a posted interrupt from becoming a pending
interrupt (input to the priority encoder). However, an interrupt can
still post even if its mask bit is zero. All INT_MSKx bits are
independent of all other INT_MSKx bits.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that becomes a pending
interrupt.
Document 38-08035 Rev. *N
When reading this register,
0 = There is no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.
When reading this register,
0 = There is no posted interrupt for the corresponding hardware.
1 = Posted interrupt for the corresponding hardware present.
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits and to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.
When reading this register,
0 = There is no posted interrupt for the corresponding hardware.
1 = Posted interrupt for the corresponding hardware present.
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.
Read/Write
Read/Write
Read/Write
Default
Default
Default
Field
Field
Field
Bit #
Bit #
Bit #
GPIO Port 1
Reserved
TCAP0
R/W
R/W
R/W
7
0
7
0
7
0
Prog Interval
Sleep Timer
Reserved
Timer
R/W
R/W
R/W
6
0
6
0
6
0
GPIO Port 3
1-ms Timer
INT1
R/W
R/W
R/W
5
0
5
0
5
0
GPIO Port 0
GPIO Port 2
USB Active
R/W
R/W
R/W
4
0
4
0
4
0
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When it is cleared, writing 1's
to an INT_CLRx register has no effect. However, writing 0's to an
INT_CLRx register, when ENSWINT is cleared, causes the
corresponding interrupt to clear. If the ENSWINT bit is set, any
0s written to the INT_CLRx registers are ignored. However, 1s
written to an INT_CLRx register, when ENSWINT is set, causes
an interrupt to post for the corresponding interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level interac-
tions that are sometimes necessary to create a hardware only
interrupt.
PS/2 Data Low
SPI Receive
USB Reset
R/W
R/W
R/W
3
0
3
0
3
0
SPI Transmit
USB EP2
INT2
R/W
R/W
R/W
CY7C63310, CY7C638xx
2
0
2
0
2
0
16-bit Counter
USB EP1
Wrap
INT0
R/W
R/W
R/W
1
0
1
0
1
0
POR/LVD
USB EP0
TCAP1
Page 53 of 86
R/W
R/W
R/W
0
0
0
0
0
0
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