SI3452C-B01-GM Silicon Laboratories Inc, SI3452C-B01-GM Datasheet - Page 9

• Manufacturer Part Number: SI3452C-B01-GM
• Description: IC POE CONTROLLER MIDSPAN 40QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3452C-B01-GM

• Package / Case: 40-QFN
• Controller Type: Power over Ethernet Controller (POE)
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 14mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Power Dissipation: 1.2 W
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3at, IEEE 802.3af
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 14 mA
• Maximum Operating Temperature: + 85 C
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 40
• Mounting: Surface Mount
• Package Type: QFN EP
• Case Length: 6mm
• Case Height: 0.83mm
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1834-5

Table 11. SMBus (I
VDD = 3.0 to 3.6 V
Description
Serial Bus Clock
Frequency
SCL High Time
SCL Low Time
SCL, SDA Rise Time
SCL, SDA Fall Time
Bus Free Time
Start Hold Time
Start Setup Time
Stop Setup Time
Data Hold Time
Data Setup Time
Time from Hardware or
Software Reset until Start
of I
Delay from Event to INT
Pin Low or from Clear-On-
Read to INT Pin High
Notes:
2
1. Not production tested (guaranteed by design).
2. All timing references measured at V
3. The Si3452 will stretch (pull down on) SCK during the ACK time period if required. The maximum SCL stretching is
C Traffic
10 µsec; so, SCL only needs to be bidirectional for I
SDA
SCL
t
BU F
2
C) Timing Specifications (see Figure 1)
Start Bit
t
ST H
Symbol
t
t
t
f
RESET
R_SCL
SC L
F_SCL
t
t
t
t
f
t
t
t
SKH
t
t
SCL
SKL
BUF
STH
STS
SPS
INT
DH
DS
D7
IL
Figure 1. I
and V
Between START and first low SCL.
t
R_SCL
Between SCL high and START
IH
Between SCL high and STOP
Between START and STOP
.
D 6
Reset to start condition
t
2
DS
C Timing Diagram
Rev. 1.2
Test Conditions
2
C bus speeds over 50 kHz.
conditions.
condition.
condition.
D5
t
F_SC L
D 4
t
D H
t
SKH
D 3
Min
600
600
600
600
200
200
1.3
1.3
20
20
—
—
0
D0
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
t
SKL
t
Stop Bit
SPS
Si3452
Max
400
300
150
100
—
—
—
—
—
—
—
—
5
Unit
kHz
ms
ms
ns
μs
ns
ns
μs
ns
ns
ns
ns
ns
9