USB2512-AEZG SMSC, USB2512-AEZG Datasheet - Page 25

• Manufacturer Part Number: USB2512-AEZG
• Description: IC USB 2.0 2PORT HUB CTLR 36-QFN
• Manufacturer: SMSC
• Type: USB HUB Controllerr

Specifications of USB2512-AEZG

• Controller Type: USB 2.0 Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 95mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Current: 130 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1050-6

USB 2.0 Hi-Speed Hub Controller
Datasheet
SMSC USB251x
NON_REM[1]
CFG_SEL[0]
CFG_SEL[1]
CFG_SEL[2]
SMBDATA /
SMBCLK /
RESET_N
SYMBOL
HS_IND /
SDA /
SCL /
BUFFER
I/OSD12
I/OSD12
TYPE
I/O12
IS
I
Table 5.2 USB251x Pin Descriptions (continued)
Serial Data signal (SDA)
Server Message Block Data signal (SMBDATA)
Non-removable Port Strap Option
If this strap is enabled by package and configuration settings (see
this pin will be sampled (in conjunction with LOCAL_PWR / SUSP_IND /
NON_REM[0]) at RESET_N negation to determine if ports [7:1] contain
permanently attached (non-removable) devices:
NON_REM[1:0] = ‘00’, All ports are removable.
NON_REM[1:0] = ‘01’, Port 1 is non-removable.
NON_REM[1:0] = ‘10’, Ports 1 & 2 are non-removable.
NON_REM[1:0] = ‘11’, When available, ports 1 2 & 3 are non-removable.
RESET Input
The system can reset the chip by driving this input low. The minimum active
low pulse is 1 μs.
Serial Clock (SCL)
System Management Bus Clock (SMBCLK)
Configuration Select: The logic state of this multifunction pin is internally
latched on the rising edge of RESET_N (RESET_N negation), and will
determine the hub configuration method as described in
Configuration
Hi-Speed Upstream Port Indicator
HS_IND: Hi-speed Indicator for upstream port connection speed.
The active state of the LED will be determined as follows:
CFG_SEL[1] = ‘0’,
HS_IND is active high,
CFG_SEL[1] = ‘1’,
HS_IND is active low,
‘Asserted’ = the hub is connected at HS
‘Negated’ = the hub is connected at FS
Configuration Programming Select
CFG_SEL[1]: The logic state of this pin is internally latched on the rising edge
of RESET_N (RESET_N negation), and will determine the hub configuration
method as described in
Configuration Programming Select
The logic state of this pin is internally latched on the rising edge of RESET_N
(RESET_N negation), and will determine the hub configuration method as
described in
pin is unavailable, then the logic is internally tied to ‘0’.
SERIAL PORT INTERFACES
Table 8.1, "Hub Configuration
Options".
DATASHEET
25
Table 8.1, "Hub Configuration
DESCRIPTION
Options". When the CFG_SEL[2]
Options".
Table 8.1, "Hub
Revision 1.1 (04-26-10)
Table
8.1),