DS21Q43-ATN Maxim Integrated Products, DS21Q43-ATN Datasheet - Page 21

• Manufacturer Part Number: DS21Q43-ATN
• Description: IC FRAMER E1 QUAD 5V 128-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q43-ATN

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 32mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
POWER-UP SEQUENCE
On power-up, after the supplies are stable, the DS21Q43A should be configured for operation by writing
to all of the internal registers (this includes the Test Registers) since the contents of the internal registers
cannot be predicted on power-up. Finally, after the RSYSCLK and TSYSCLK inputs are stable, the ESR
bit should be toggled from a 0 to a 1 and then back to 0 (this step can be skipped if the elastic store is not
being used).
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS21Q43A,
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR).
(MSB)
TESE
SYMBOL
TCBFS
TIRFS
TBCS
TESE
ESR
-
-
-
TCBFS
POSITION
CCR3.7
CCR3.6
CCR3.5
CCR3.4
CCR3.3
CCR3.2
CCR3.1
CCR3.0
TIRFS
NAME AND DESCRIPTION
Transmit Side Elastic Store Enable.
0=elastic store is bypassed.
1=elastic store is enabled.
Transmit Channel Blocking Registers (TCBR) Function
Select.
0=TCBRs define the operation of the TCHBLK output pin.
1=TCBRs define which signaling bits are to be inserted.
Transmit Idle Registers (TIR) Function Select.
0=TIRs define in which channels to insert idle code.
1=TIRs define in which channels to insert data from RSER.
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. Should be toggled after
RSYSCLK and TSYSCLK have been applied and are stable.
Must be set and cleared again for a subsequent reset. Do not
leave this bit set high.
Not Assigned. Should be set to 0 when written.
Not Assigned. Should be set to 0 when written.
Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
Not Assigned. Should be set to 0 when written.
ESR
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LIRST
-
TBCS
DS21Q43A
(LSB)
-