AD9958BCPZ Analog Devices Inc, AD9958BCPZ Datasheet - Page 37

• Manufacturer Part Number: AD9958BCPZ
• Description: IC DDS DUAL 500MSPS DAC 56LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9958BCPZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186)
• Resolution (bits): 10 b
• Master Fclk: 500MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.71 V ~ 1.96 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Pll Type: Frequency Synthesis
• Frequency: 500MHz
• Supply Current: 105mA
• Supply Voltage Range: 1.71V To 1.89V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 56
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9958/PCBZ - BOARD EVALUATION FOR AD9958
• Lead Free Status / Rohs Status: Compliant

Table 29. Channel Register Map
Register
Name
(Serial
Address)
Channel
Function
Register
(CFR)
(0x03)
Channel
Frequency
Tuning
Word 0
(CFTW0)
(0x04)
Channel
Phase
Offset
Word 0
(CPOW0)
(0x05)
Amplitude
Control
Register
(ACR)
(0x06)
Linear
Sweep
Ramp
Rate
(LSRR)
(0x07)
LSR Rising
Delta
Word
(RDW)
(0x08)
LSR Falling
Delta
Word
(FDW)
(0x09)
1
2
There are two sets of channel registers and profile registers, one per channel. This is not shown in the Table 29 or Table 30 because the addresses of all channel
registers and profile registers are the same for each channel. Therefore, the channel enable bits (CSR[7:6]) determine if the channel registers and/or profile registers of
each channel are written to or not.
The clear phase accumulator bit (CFR[1]) is set to Logic 1 after a master reset. It self-clears or is set to Logic 0 when an I/O update is asserted.
1
1
1
1
1
1
Bit
Range
[23:16]
[15:8]
[7:0]
[31:24]
[23:16]
[15:8]
[7:0]
[15:8]
[7:0]
[23:16]
[15:8]
[7:0]
[15:8]
[7:0]
[31:24]
[23:16]
[15:8]
[7:0]
[31:24]
[23:16]
[15:8]
[7:0]
Digital
Bit 7
(MSB)
Linear
sweep
no-dwell
power-
down
Amplitude freq. phase
Increment/decrement
(AFP) select[23:22]
step size[15:14]
Open[15:14]
Bit 6
Linear
sweep
enable
DAC
power-
down
Bit 5
Load SRR at
I/O_UPDATE
Matched
pipe delays
active
Open
Falling sweep ramp rate (FSRR)[15:8]
Rev. A | Page 37 of 44
Bit 4
Autoclear
sweep
accumulator
Amplitude
multiplier
enable
Rising sweep ramp rate (RSRR)[7:0]
Frequency Tuning Word 0[31:24]
Frequency Tuning Word 0[23:16]
Frequency Tuning Word 0[15:8]
Frequency Tuning Word 0[7:0]
Amplitude Ramp Rate[23:16]
Amplitude scale factor[7:0]
Falling delta word[31:24]
Falling delta word[23:16]
Phase Offset Word 0[7:0]
Rising delta word[31:24]
Rising delta word[23:16]
Falling delta word[15:8]
Rising delta word[15:8]
Falling delta word[7:0]
Rising delta word[7:0]
Open[12:11]
Bit 3
Clear sweep
accumulator
Ramp-up/
ramp-down
enable
Phase Offset Word 0[13:8]
Open[21:16]
Bit 2
Must be 0
Autoclear
phase
accumulator
Load ARR at
I/O_UPDATE
Bit 1
Clear phase
accumulator
DAC full-scale current
Amplitude scale
control[9:8]
factor[9:8]
2
Bit 0
(LSB)
Sine
wave
output
enable
AD9958
0x00
0x00
N/A
N/A
0x00
0x00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Default
Value
0x03
0x02
N/A
0x00
0x00
N/A