AD9854ASTZ Analog Devices Inc, AD9854ASTZ Datasheet - Page 25

• Manufacturer Part Number: AD9854ASTZ
• Description: IC DDS QUADRATURE CMOS 80-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9854ASTZ

• Package / Case: 80-LQFP
• Resolution (bits): 12 b
• Master Fclk: 300MHz
• Tuning Word Width (bits): 48 b
• Voltage - Supply: 3.14 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Supply Voltage Range: 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 80
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 9854
• Ic Function: Direct Digital Synthesizer
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9854/PCBZ - BOARD EVAL FOR AD9854
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

The AD9854 permits precise, internally generated linear, or
externally programmed nonlinear, pulsed or continuous FM
over the complete frequency range, duration, frequency
resolution, and sweep direction(s). All of these are user
programmable. Figure 44 shows a block diagram of the FM
chirp components.
Basic FM Chirp Programming Steps
1.
2.
3.
When programming is complete, an I/O update pulse at Pin 20
engages the program commands.
The necessity for a twos complement delta frequency word is to
define the direction in which the FM chirp moves. If the 48-bit
delta frequency word is negative (MSB is high), the incremental
frequency changes are in a negative direction from FTW1. If the
48-bit word is positive (MSB is low), the incremental frequency
changes are in a positive direction from FTW1.
It is important to note that FTW1 is only a starting point for FM
chirp. There is no built-in restraint requiring a return to FTW1.
Once the FM chirp begins, it is free to move (under program
control) within the Nyquist bandwidth (dc to one-half the system
clock). However, instant return to FTW1 can be easily achieved.
COMPLEMENT)
WORD (TWOS
48-BIT DELTA
FREQUENCY
HOLD
Program a start frequency into Frequency Tuning Word 1
(FTW1) at Parallel Register Address 4 hex to Parallel Register
Address 9 hex.
Program the frequency step resolution into the 48-bit,
twos complement delta frequency word (Parallel Register
Address 10 hex to Parallel Register Address 15 hex).
Program the rate of change (time at each frequency) into
the 20-bit ramp rate clock (Parallel Register Address 1A hex
to Parallel Register Address 1C hex).
ACCUMULATOR
FREQUENCY
RAMP RATE
CLOCK
20-BIT
Figure 44. FM Chirp Components
CLR ACC1
FREQUENCY
WORD 1
TUNING
ADDER
ACCUMULATOR
PHASE
SYSTEM
CLOCK
CLR ACC2
OUT
Rev. E | Page 25 of 52
Two control bits (CLR ACC1 and CLR ACC2) are available
in the FM chirp mode that allow the return to the beginning
frequency, FTW1, or to 0 Hz. When the CLR ACC1 bit
(Register Address 1F hex) is set high, the 48-bit frequency
accumulator (ACC1) output is cleared with a retriggerable
one-shot pulse of one system clock duration. The 48-bit delta
frequency word input to the accumulator is unaffected by the
CLR ACC1 bit. If the CLR ACC1 bit is held high, a one-shot
pulse is delivered to the frequency accumulator (ACC1) on every
rising edge of the I/O update clock. The effect is to interrupt the
current chirp, reset the frequency to that programmed into FTW1,
and continue the chirp at the previously programmed rate and
direction. Clearing the output of the frequency accumulator in
the chirp mode is illustrated in Figure 45. Shown in the diagram
is the I/O update clock, which is either user supplied or internally
generated.
Alternatively, the CLR ACC2 control bit (Register Address 1F hex)
is available to clear both the frequency accumulator (ACC1)
and the phase accumulator (ACC2). When this bit is set high,
the output of the phase accumulator results in 0 Hz output from
the DDS. As long as this bit is set high, the frequency and phase
accumulators are cleared, resulting in 0 Hz output. To return to
the previous DDS operation, CLR ACC2 must be set to logic
low. This bit is useful in generating pulsed FM.
Figure 46 illustrates the effect of the CLR ACC2 bit on the DDS
output frequency. Note that reprogramming the registers while
the CLR ACC2 bit is high allows a new FTW1 frequency and
slope to be loaded.
Another function that is available only in chirp mode is the
HOLD pin (Pin 29). This function stops the clock signal to the
ramp rate counter, halting any further clocking pulses to
the frequency accumulator, ACC1. The effect is to halt the chirp
at the frequency existing just before the HOLD pin is pulled
high. When Pin 29 is returned low, the clock and chirp resumes.
During a hold condition, the user can change the programming
registers; however, the ramp rate counter must resume operation at
its previous rate until a count of 0 is obtained before a new ramp
rate count can be loaded. Figure 47 shows the effect of the hold
function on the DDS output frequency.
AD9854