CY7C9689A-AXC Cypress Semiconductor Corp, CY7C9689A-AXC Datasheet - Page 14

• Manufacturer Part Number: CY7C9689A-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: Transceiverr

Specifications of CY7C9689A-AXC

• Package / Case: 100-LQFP
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: PHY
• Interface Type: Parallel
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2 V
• Supply Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Msl: MSL 3 - 168 Hours
• No. Of Receivers: 2
• Rohs Compliant: Yes
• Frequency Max: 50MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document #: 38-02020 Rev. *E
CY7C9689A TAXI HOTLink Transceiver
Block Diagram Description
Transmit Input/Output Register
The CY7C9689A provides a synchronous interface for data
and command inputs, instead of the TAXI’s asynchronous
strobed interface. The Transmit Input Register, shown in
Figure
the HOTLink Transmitter, and allows the input timing to be
made compatible with asynchronous or synchronous host
system buses. These buses can take the form of external
FIFOs, state machines, or other control structures. Data and
command present on the TXDATA[9:0] and TXSC/D inputs are
captured at the rising edge of the selected sample clock. The
transmit data bus bit-assignments vary depending on the data
encoding and bus-width selected. These bus bit-assignments
are shown in
different signals. Note that the function of several of these
signals changes in different operating modes. The logical
sense of the enable and FIFO flag signals depends on the
intended interface convention and is set by the EXTFIFO pin.
The transmit interface supports both synchronous and
asynchronous clocking modes, each supporting both UTOPIA
and Cascade timing models. The selection of the specific
Table 1. Transmit Input Bus Signal Map
Notes
1. All open cells are ignored.
2. When ENCBYP is HIGH and BYTE8/10 is HIGH, transmitted bit order is the encoded form (MSB to LSB) of TXDATA[7,6,5,4] and TXDATA[3,2,1,0] or TXC-
3. When ENCBYP is HIGH and BYTE8/10 is LOW, transmitted bit order is the encoded form (MSB to LSB) of TXDATA[8,7,6,5,4] and TXDATA[9,3,2,1,0] or
4. When ENCBYP is LOW and BYTE8/10 is HIGH, the transmitted bit order is (LSB to MSB) TXD[0,1,2,3,4,5,6,7,8,9].
5. When ENCBYP is LOW and BYTE8/10 is LOW, the transmitted bit order is (LSB to MSB) TXD[0,1,2,3,4,5,6,7,8,9,11,10].
TXDATA Bus Input Bit
TXDATA[8]/TXCMD[3]
TXDATA[9]/TXCMD[2]
MD[3,2,1,0] as selected by TXSC/D.
TXCMD[1,0] as selected by TXSC/D.
2, captures the data and command to be processed by
TXDATA[0]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
TXCMD[1]
TXCMD[0]
TXSC/D
Table
1, and list the functional names of these
Character Stream
Encoded 8-bit
TXDATA[0]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
TXCMD[3]
TXCMD[2]
TXCMD[1]
TXCMD[0]
TXSC/D
[2]
Pre-encoded 10-bit
Character Stream
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXD[8]
TXD[9]
Transmit Encoder Mode
clocking mode is determined by the RANGESEL and SPDSEL
inputs and the FIFO Bypass (FIFOBYP) signal.
TXDATA[7:0]
TXCMD[3:0]
[4]
To Encoder
Block
Transmit Input Register
12
Figure 2. Transmit Input Register
Character Stream
TXSC/D
Encoded 10-bit
TXDATA[9]
TXDATA[0]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
TXDATA[8]
TXCMD[1]
TXCMD[0]
TXSC/D
Transmit FIFO
14
[1]
TXEN
[3]
CE
[3]
Pre-encoded 12-bit
Character Stream
CY7C9689A
TXCLK
TXD[10]
TXD[0]
TXD[11]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXD[8]
TXD[9]
Page 14 of 51
REFCLK
[5]
[5]
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