CY7C9689A-AXC Cypress Semiconductor Corp, CY7C9689A-AXC Datasheet - Page 41

• Manufacturer Part Number: CY7C9689A-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: Transceiverr

Specifications of CY7C9689A-AXC

• Package / Case: 100-LQFP
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: PHY
• Interface Type: Parallel
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2 V
• Supply Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Msl: MSL 3 - 168 Hours
• No. Of Receivers: 2
• Rohs Compliant: Yes
• Frequency Max: 50MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document #: 38-02020 Rev. *E
When the Transmit FIFO is enabled (FIFOBYP is HIGH) and
CE is sampled LOW by the rising edge of TXCLK, the output
drivers for the TXFULL and TXEMPTY FIFO flags are
enabled. When CE is sampled HIGH by the rising edge of
TXCLK, these same output drivers are disabled.
When the Transmit FIFO is bypassed (FIFOBYP is LOW and
not in byte-packed mode) and CE is sampled LOW by the
rising edge of REFCLK, the output drivers for the TXFULL and
TXEMPTY FIFO flags are enabled. When CE is sampled
HIGH by the rising edge of REFCLK, the FIFO flag output
drivers are disabled.
When CE is sampled LOW by the rising edge of RXCLK (input
or output), the output drivers for the RXFULL and RXEMPTY
FIFO flags are enabled. When CE is sampled HIGH by the
rising edge of RXCLK, the FIFO flag output drivers are
disabled.
Device Selection
The concept of selection is used to control the access to the
transmit and receive parallel-data ports of the device. There
are three primary types of selection:
In addition to these normal selection types, there are two
additional sequences that are used to control the internal
Transmit and Receive FIFOs reset operations, and to control
read/write access to the Serial Address Register:
Of these operations, the transmit data selection and transmit
reset sequence are mutually exclusive and cannot exist at the
same time. The receive data selection and receive reset
sequence are also mutually exclusive and cannot exist at the
same time. Either transmit operation can exist at the same
time as either receive operation.
• Transmit data selection (with and without internal Transmit
• Receive data selection (with and without internal Receive
• Continuous selection (for either or both transmit and receive
• Transmit reset sequence
• Receive reset sequence.
FIFO)
FIFO)
interfaces).
All normal forms of selection require that an Chip Enable must
be asserted (CE sampled LOW) either at the same time as the
selection control signal being sampled asserted, or one or
more clock cycles prior to the selection control signal being
sampled asserted.
Transmit Data Selection
Asynchronous With Shared Bus Timing and Control
(Transmit FIFO Enabled)
When CE is sampled LOW and TXRST is sampled HIGH by
the rising edge of TXCLK, a Tx_Match condition is generated.
This Tx_Match condition continues until CE is sampled HIGH
or TXRST is sampled LOW at the rising edge of TXCLK. When
a Tx_Match (or Tx_RstMatch) condition is present, the
TXEMPTY and TXFULL output drivers are enabled. When a
Tx_Match (or Tx_RstMatch) condition is not present, these
same drivers are disabled (High-Z).
The selection state of the Transmit FIFO is entered when a
Tx_Match condition is present, and TXEN transitions from
HIGH to LOW. Once selected, the Transmit FIFO remains
selected until TXEN is sampled HIGH by the rising edge of
TXCLK. In the selected state, data present on the TXDATA
inputs is captured and stored in the Transmit FIFO. This
transmit interface selection process is shown in
Synchronous With Shared Bus Timing and Control
(Transmit FIFO Bypassed)
When the Transmit FIFO is bypassed (FIFOBYP is LOW and
not in byte-packed mode), the CY7C9689A must still be
selected to write data into the Transmit Input Register.
When CE is sampled LOW and TXRST is sampled HIGH by
the rising edge of REFCLK, a Tx_Match condition is
generated. This Tx_Match condition continues until CE is
sampled HIGH or TXRST is sampled LOW at the rising edge
of REFCLK. When a Tx_Match (or Tx_RstMatch) condition is
present, the TXEMPTY and TXFULL output drivers are
enabled (with the Transmit FIFO bypassed, the status flags
normally indicate an Empty condition). When a Tx_Match (or
Tx_RstMatch) condition is not present, these same drivers are
disabled (High-Z).
CY7C9689A
Page 41 of 51
Figure
8.
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