PIC16F628A-I/P Microchip Technology Inc., PIC16F628A-I/P Datasheet - Page 62

• Manufacturer Part Number: PIC16F628A-I/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628A-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F62X
EXAMPLE 10-1:
10.2
The full range of V
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 10-1) keep V
The Voltage Reference is V
the V
tested absolute accuracy of the Voltage Reference can
be found in Table 17-2.
10.3
When the device wakes-up from SLEEP through an
interrupt or a Watchdog Timer timeout, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 10-2:
TABLE 10-1:
DS40300C-page 60
MOVLW
MOVWF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
9Fh
1Fh
85h
Note 1: — = Unimplemented, read as ‘0’.
Address
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
REF
Voltage Reference Accuracy/Error
Operation During SLEEP
output changes with fluctuations in V
VRCON
CMCON C2OUT C1OUT
TRISA
Name
0x02
CMCON
STATUS,RP0
0x07
TRISA
0xA6
VRCON
STATUS,RP0
DELAY10
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
SS
Module
V
REF
TRISA7 TRISA6 TRISA5 TRISA4
to V
REF
VREN
Bit 7
VOLTAGE REFERENCE
CONFIGURATION
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
from approaching V
DD
Voltage
Reference
Output
Impedance
DD
cannot be realized due to
; 4 Inputs Muxed
; to 2 comps.
; go to Bank 1
; RA3-RA0 are
; outputs
; enable V
; low range
; set V
; go to Bank 0
; 10µs delay
VROE
Bit 6
derived and therefore,
R
(1)
R
<3:0>=6
C2INV
Bit 5
VRR
REF
RA2
SS
DD
or V
C1INV
Bit 4
. The
—
Preliminary
DD
.
TRISA3
Bit 3
VR3
CIS
10.4
A device RESET disables the Voltage Reference by
clearing bit V
disconnects the reference from the RA2 pin by clearing
bit V
range by clearing bit V
value select bits, VRCON<3:0>, are also cleared.
10.5
The
independently of the Comparator module. The output
of the reference generator may be connected to the
RA2 pin if the TRISA<2> bit is set and the V
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with V
current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
V
technique.
REF
TRISA2
Bit 2
CM2
VR2
ROE
. Figure 10-2 shows an example buffering
Op Amp
+
Voltage
Effects of a RESET
Connection Considerations
(VRCON<6>) and selects the high voltage
TRISA1
Bit 1
CM1
VR1
REN
Reference
(VRCON<7>). This RESET also
V
TRISA0
REF
REF
Bit 0
CM0
VR0
 2003 Microchip Technology Inc.
RR
Output
enabled will also increase
(VRCON<5>). The V
000- 0000 000- 0000
0000 0000 0000 0000
1111 1111 1111 1111
Value On
POR
module
Value On
All Other
RESETS
operates
ROE
REF
bit,