DS1307+ Dallas Semiconductor, DS1307+ Datasheet - Page 11

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DS1307+

Manufacturer Part Number
DS1307+
Description
Clock, Real Time; PDIP; 8 Pins; -0.5 to +7.0 V; 0.7 V (Max.); +0.8 V (Max.)
Manufacturer
Dallas Semiconductor
Datasheet

Specifications of DS1307+

Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
Figure 3. Data Transfer on I
Depending upon the state of the R/W bit, two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge
bit after each received byte. Data is transferred with the most significant bit (MSB) first.
transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave
transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received byte, a “not acknowledge” is returned.
The master device generates all the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial transfer, the bus will not be released. Data is
transferred with the most significant bit (MSB) first.
SDA
SCL
CONDITION
START
MSB
1
2
2
C Serial Bus
6
7
DIRECTION
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
R/W
BIT
8
ACK
9
11 of 15
1
REPEATED IF MORE BYTES
ARE TRANSFERED
2
DS1307 64 x 8, Serial, I
SIGNAL FROM RECEIVER
3-7
ACKNOWLEDGEMENT
8
ACK
9
2
C Real-Time Clock
CONDITION
CONDITION
REPEATED
START
STOP
OR

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