DS1307+ Dallas Semiconductor, DS1307+ Datasheet - Page 8

• Manufacturer Part Number: DS1307+
• Description: Clock, Real Time; PDIP; 8 Pins; -0.5 to +7.0 V; 0.7 V (Max.); +0.8 V (Max.)
• Manufacturer: Dallas Semiconductor

Specifications of DS1307+

• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. Table 2 shows
the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in the BCD format. The day-of-week register
increments at midnight. Values that correspond to the day of week are user-defined but must be
sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.) Illogical time and date entries
result in undefined operation. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set to 1, the
oscillator is disabled. When cleared to 0, the oscillator is enabled.
Note that the initial power-on state of all registers is not defined. Therefore, it is important to
enable the oscillator (CH bit = 0) during initial configuration.
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5
is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20 to
23 hours). The hours value must be re-entered whenever the 12/24-hour mode bit is changed.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the time and date registers, the user buffers are
synchronized to the internal registers on any I
secondary registers while the clock continues to run. This eliminates the need to re-read the registers in
case the internal registers update during a read. The divider chain is reset whenever the seconds register is
written. Write transfers occur on the I
to avoid rollover issues, the remaining time and date registers must be written within one second.
Table 2. Timekeeper Registers
0 = Always reads back as 0.
ADDRESS
08H-3FH
00H
01H
02H
03H
04H
05H
06H
07H
BIT 7
OUT
CH
0
0
0
0
0
BIT 6
12
24
0
0
0
0
10 Year
10 Seconds
10 Minutes
BIT 5
Hour
PM/
AM
10
0
0
0
10 Date
2
C acknowledge from the DS1307. Once the divider chain is reset,
SQWE
Month
BIT 4
Hour
10
10
0
2
8 of 15
BIT 3
C START. The time information is read from these
0
0
BIT 2
0
Seconds
Minutes
Month
Hours
Date
Year
DS1307 64 x 8, Serial, I
BIT 1
DAY
RS1
BIT 0
RS0
FUNCTION
Seconds
Minutes
Control
Month
Hours
56 x 8
RAM
Year
Date
Day
2
C Real-Time Clock
00H–FFH
+AM/PM
RANGE
00–59
00–59
00–23
01–07
01–31
01–12
00–99
1–12
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