LAN8720AI-CP SMSC, LAN8720AI-CP Datasheet - Page 31

• Manufacturer Part Number: LAN8720AI-CP
• Description: TXRX ETHERNET 10/100 RMII 24QFN
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8720AI-CP

• Number Of Drivers/receivers: 4/4
• Protocol: RMII
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Product: Ethernet Transceivers
• Standard Supported: 802.3, 802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1084

Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
SMSC LAN8720A/LAN8720Ai
3.7
3.7.1
3.7.2
Configuration straps allow various features of the device to be automatically configured to user defined
values. Configuration straps are latched upon Power-On Reset (POR) and pin reset (nRST).
Configuration straps include internal resistors in order to prevent the signal from floating when
unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down
resistor should be used to augment the internal resistor to ensure that it reaches the required voltage
level prior to latching. The internal resistor can also be overridden by the addition of an external
resistor.
Note: The system designer must guarantee that configuration strap pins meet the timing
Note: When externally pulling configuration straps high, the strap should be tied to VDDIO, except
PHYAD[0]: PHY Address Configuration
The PHYAD0 bit is driven high or low to give each PHY a unique address. This address is latched into
an internal register at the end of a hardware reset (default = 0b). In a multi-PHY application (such as
a repeater), the controller is able to manage each PHY via the unique address. Each PHY checks
each management data frame for a matching address in the relevant bits. When a match is recognized,
the PHY responds to that particular frame. The PHY address is also used to seed the scrambler. In a
multi-PHY application, this ensures that the scramblers are out of synchronization and disperses the
electromagnetic radiation across the frequency spectrum.
The device’s SMI address may be configured using hardware configuration to either the value 0 or 1.
The user can configure the PHY address using Software Configuration if an address greater than 1 is
required. The PHY address can be written (after SMI communication at some address is established)
using the
multiplexed with the RXER pin.
MODE[2:0]: Mode Configuration
The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the
nRST pin is deasserted, the register bit values are loaded according to the MODE[2:0] configuration
straps. The 10/100 digital block is then configured by the register bit values. When a soft reset occurs
via the
controlled by the register bit values and the MODE[2:0] configuration straps have no affect.
The device’s mode may be configured using the hardware configuration straps as summarized in
Table
Configuration Straps
3.4. The user may configure the transceiver mode by writing the SMI registers.
requirements specified in
page
the device may capture incorrect strap values.
for REGOFF and nINTSEL which should be tied to VDD2A.
Soft Reset
PHYAD
70. If configuration strap pins are not at the correct voltage level prior to being latched,
bits of the
bit of the
Basic Control
Special Modes
Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on
DATASHEET
31
Register, the configuration of the 10/100 digital block is
Register. The PHYAD0 hardware configuration strap is
Revision 1.2 (11-10-10)