PIC12F629-I/SN Microchip Technology Inc., PIC12F629-I/SN Datasheet - Page 65

• Manufacturer Part Number: PIC12F629-I/SN
• Description: 8 PIN, 1.75 KB FLASH, 64 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F629-I/SN

• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin SOIC-N
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.4.1
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, of
falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from SLEEP if the
INTE bit was set prior to going into SLEEP. The status
of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 9.7 for details on SLEEP and Figure 9-13 for
timing of wake-up from SLEEP through GP2/INT
interrupt.
FIGURE 9-11:
 2003 Microchip Technology Inc.
INSTRUCTION FLOW
Note:
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF Flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
Executed
Instruction
Fetched
PC
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
on
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
GP2/INT INTERRUPT
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3
the
Q1
Inst (PC-1)
GP2/INT
Inst (PC)
INT PIN INTERRUPT TIMING
1
Q2
PC
Q3
4
pin,
Q4
5
Q1
the
Inst (PC+1)
Inst (PC)
Q2
1
INTF
PC+1
CY
Q3
. Synchronous latency = 3 T
bit
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
9.4.2
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 4.0.
9.4.3
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOC register.
9.4.4
See Section 6.9 for description of comparator interrupt.
9.4.5
After a conversion is complete, the ADIF flag (PIR<6>)
is set. The interrupt can be enabled/disabled by setting
or clearing ADIE (PIE<6>).
See Section 7.0 for operation of the A/D converter
interrupt.
PC+1
—
Note:
Q3
enabled/disabled
Q4
CY
2
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
, where T
TMR0 INTERRUPT
GPIO INTERRUPT
COMPARATOR INTERRUPT
A/D CONVERTER INTERRUPT
Q1
Dummy Cycle
PIC12F629/675
Inst (0004h)
Q2
CY
0004h
= instruction cycle time. Latency
Q3
by
Q4
setting/clearing
Q1
DS41190C-page 63
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
T0IE