PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 295

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
REG
W
REG
W
REG
Q1
PIC18F6520/8520/6620/8620/6720/8720
=
=
=
=
=
=
register ‘f’
Rotate Right f (no carry)
[ label ]
0
d
a
(f<n>)
(f<0>)
N, Z
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
1110 1011
?
1101 0111
1110 1011
1101 0111
f
[0,1]
[0,1]
255
dest<n-1>,
dest<7>
REG, 1, 0
REG, 0, 0
RRNCF
00da
Process
Data
Q3
register f
ffff
f [,d [,a]
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ‘f’
Set f
[ label ] SETF
0
a
FFh
None
The contents of the specified
register are set to FFh. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
1
1
SETF
Read
0110
Q2
=
=
f
[0,1]
255
f
0x5A
0xFF
100a
Process
Data
REG,1
Q3
DS39609B-page 293
f [,a]
ffff
register ‘f’
Write
Q4
ffff