MAX3462ESA+ Maxim Integrated Products, MAX3462ESA+ Datasheet - Page 9

• Manufacturer Part Number: MAX3462ESA+
• Description: IC TXRX RS485/422 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of MAX3462ESA+

• Number Of Drivers/receivers: 1/1
• Protocol: RS422, RS485
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Data Rate: 20000 Kbps
• Propagation Delay Time Ns: 20 ns
• Operating Supply Voltage: 5 V
• Supply Current: 2.5 mA
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5 V
• Maximum Power Dissipation: 471 mW
• Mounting Style: SMD/SMT
• Output Current: +/- 250 mA
• Output Voltage: - 8 V to + 13 V
• Product: RS-422
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX3460–MAX3464 high-speed transceivers for
RS-485/RS-422 communication contain one driver and
one receiver. These devices feature true fail-safe cir-
cuitry, which guarantees a logic-high receiver output
when the receiver inputs are open or shorted, or when
they are connected to a terminated transmission line
with all drivers disabled (see the True Fail-Safe sec-
tion). The MAX3460–MAX3464’s driver slew rates allow
transmit speeds up to 20Mbps.
The MAX3463 and MAX3464 are half-duplex trans-
ceivers, while the MAX3460, MAX3461, and MAX3462
are full-duplex transceivers. All of these parts operate
from a single +5V supply. Drivers are output short-cir-
cuit current limited. Thermal shutdown circuitry protects
drivers against excessive power dissipation. When acti-
vated, the thermal shutdown circuitry places the driver
outputs into a high-impedance state. The MAX3460
and MAX3463 devices have a hot-swap input structure
that prevents disturbances on the differential signal
lines when a circuit board is plugged into a “hot” back-
plane (see Hot Swap section). All devices have output
levels that are compatible with Profibus standards.
The MAX3460–MAX3464 guarantee a logic-high receiv-
er output when the receiver inputs are shorted or open,
or when they are connected to a terminated transmis-
sion line with all drivers disabled. This is done by set-
ting the receiver threshold between -50mV and
-200mV. If the differential receiver input voltage (A - B)
is greater than or equal to -50mV, RO is logic high. If A
- B is less than or equal to -200mV, RO is logic low. In
the case of a terminated bus with all transmitters dis-
abled, the receiver’s differential input voltage is pulled
to 0V by the termination. With the receiver thresholds of
the MAX3460–MAX3464, this results in a logic high with
a 50mV minimum noise margin. Unlike previous true
fail-safe devices, the -50mV to -200mV threshold com-
plies with the ±200mV EIA/TIA-485 standard.
When circuit boards are inserted into a “hot” or pow-
ered backplane, disturbances to the enable and differ-
ential receiver inputs can lead to data errors. Upon
initial circuit board insertion, the processor undergoes
its power-up sequence. During this period, the output
drivers are high impedance and are unable to drive the
DE input of the MAX3460/MAX3463 to a defined logic
_______________________________________________________________________________________
+5V, Fail-Safe, 20Mbps, Profibus RS-485/
Detailed Description
Hot-Swap Capability
True Fail-Safe
Hot-Swap Inputs
level. Leakage currents up to 10µA from the high-
impedance output could cause DE to drift to an incor-
rect logic state. Additionally, parasitic circuit board
capacitance could cause coupling of V
DE. These factors could improperly enable the driver.
When V
low for around 15µs. After the initial power-up
sequence, the pulldown circuit becomes transparent,
resetting the hot-swap tolerable input.
The MAX3460/MAX3463 enable inputs feature hot-swap
capability. At the input there are two NMOS devices, M1
and M2 (Figure 4). When V
15µs timer turns on M2 and sets the SR latch, which
also turns on M1. Transistors M2, a 2mA current sink,
and M1, a 100µA current sink, pull DE to GND through a
5.6kΩ resistor. M2 is designed to pull DE to the disabled
state against an external parasitic capacitance up to
100pF that can drive DE high. After 15µs, the timer
deactivates M2 while M1 remains on, holding DE low
against three-state leakages that can drive DE high. M1
remains on until an external source overcomes the
required input current. At this time, the SR latch resets
and M1 turns off. When M1 turns off, DE reverts to a
standard, high-impedance CMOS input. Whenever V
drops below 1V, the hot-swap input is reset.
For RE there is a complimentary circuit employing two
PMOS devices pulling RE to V
Figure 4. Simplified Structure of the Driver Enable Pin (DE)
EN
TIMER
RS-422 Transceivers
V
CC
CC
5.6kΩ
rises, an internal pulldown circuit holds DE
TIMER
M1
100µA
15µs
2mA
CC
M2
Hot-Swap Input Circuitry
CC
ramps from 0, an internal
.
CC
or GND to
(HOT SWAP)
DE
CC
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