DS26521LN+ Maxim Integrated Products, DS26521LN+ Datasheet - Page 81

• Manufacturer Part Number: DS26521LN+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521LN+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.
Thirteen address bits are used to control the settings of the registers. The address map is compatible with the
Dallas Semiconductor dual framer product, DS26522.
The registers control functions of the framers, LIU, and BERT within the DS26521. Global registers (applicable to
the transceiver and BERT) are located within the address space of the framer.
The register details are provided in the following tables. Thirteen address bits are needed to decode the register
range. However, address bits A9, A10, and A11 are internally pulled to ground and do not come out to a pin. These
bits are not needed to access any available register on the DS26521. The address range was mapped this way to
preserve software compatibility with the register maps of the TEX-series transceiver family of devices (DS26528,
DS26524, and DS26522). This allows for reuse of software developed for the DS26528 octal, for example, without
remapping the registers.
All interrupt information register bits are real-time bits that clear once the appropriate interrupt has been serviced
and cleared, as long as no additional, unmasked interrupt condition is present in the associated status register.
All latched status bits must be cleared by the host writing a 1 to the bit location of the interrupt condition that has
been serviced. Latched status bits that have been masked via interrupt mask registers are masked from the
interrupt information registers.
9.1
Table 9-1. Register Address Ranges
*
A9, A10, and A11 are internally pulled low to provide software compatibility with other TEX-series transceivers.
Registers
Transmit
Receive
BLOCK
Framer
Framer
Global
BERT
TEST
LIU
DEVICE REGISTERS
Register Listings
0000–00EF
00F0–00FF
0100–01EF
1000–1017
1018–101F
1100–110F
ADDRESS
(IN HEX)
RANGE
A12
0
1
0
0
1
1
A8
0
0
1
0
0
1
A[7:4]
0000
1111
0000
0000
0000
0000
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ADDRESS RANGE (IN BINARY)*
A[3:0]
0000
0000
0000
0000
1000
0000
A12
DS26521 Single T1/E1/J1 Transceiver
0
0
0
1
1
1
A8
0
0
1
0
0
1
A[7:4]
1110
1111
1110
0000
0001
0000
A[3:0]
1111
1111
1111
0111
1111
1111