DSPIC33FJ256GP710-I/PT Microchip Technology Inc., DSPIC33FJ256GP710-I/PT Datasheet - Page 213

• Manufacturer Part Number: DSPIC33FJ256GP710-I/PT
• Description: DSP, 16-Bit, 256KB Flash, 30KB RAM, 85 I/O, TQFP-100
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ256GP710-I/PT

• A/d Inputs: 32-Channels, 12-Bit
• Comparators: 8
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 85
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 30K Bytes
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6
• Lead Free Status / Rohs Status: RoHS Compliant part

REGISTER 17-3:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN
R/W-0
U-0
—
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
Unimplemented: This bit must not be set to ‘1’ by the user application.
SPIFSD
R/W-0
U-0
—
SPIxCON2: SPIx CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
FRMPOL
R/W-0
U-0
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
FRMDLY
dsPIC33F
R/W-0
U-0
—
DS70165E-page 211
U-0
U-0
—
—
bit 8
bit 0