PIC16F73-I/SO Microchip Technology Inc., PIC16F73-I/SO Datasheet - Page 78

• Manufacturer Part Number: PIC16F73-I/SO
• Description: 28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F73-I/SO

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X
FIGURE 10-5:
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
TABLE 10-6:
DS30325B-page 76
Address
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
INTCON
PIR1
RCSTA
RCREG USART Receive Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
PSPIE
PSPIF
START
SPEN
CSRC
ASYNCHRONOUS RECEPTION
Bit 7
bit
GIE
(1)
(1)
bit0
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
bit1
TMR0IE
SREN
TXEN
RCIF
RCIE
Bit 5
bit7/8
CREN
SYNC
INTE
TXIE
Bit 4
TXIF
STOP
bit
Word 1
RCREG
START
SSPIF CCP1IF
SSPIE CCP1IE TMR2IE
RBIE
Bit 3
bit
—
—
bit0
6.
7.
8.
9.
10. If using interrupts, ensure that GIE and PEIE in
TMR0IF
BRGH
FERR
Bit 2
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
the INTCON register are set.
TMR2IF
bit7/8 STOP
OERR
TRMT
Word 2
RCREG
INTF
Bit 1
bit
TMR1IF
TMR1IE
RX9D
TX9D
RBIF
Bit 0
START
 2002 Microchip Technology Inc.
bit
0000 000x
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
bit7/8
STOP
bit
0000 000u
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
RESETS
all other