PIC16F84A-04I/P Microchip Technology Inc., PIC16F84A-04I/P Datasheet - Page 21

• Manufacturer Part Number: PIC16F84A-04I/P
• Description: 18 PIN, 1.75 KB FLASH, 68 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F84A-04I/P

• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 68 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt-on-overflow from FFh to 00h
Figure 5-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the
(DS33023).
5.1
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
FIGURE 5-1:
2001 Microchip Technology Inc.
RA4/T0CKI
pin
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
PICmicro™
Timer0
TIMER0 MODULE
Timer0 Operation
2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).
T0SE
Source
F
OSC
Mid-Range
TIMER0 BLOCK DIAGRAM
/4
Edge
T0CS
0
Reference
Select
1
PS2, PS1, PS0
bit,
Programmable
Prescaler
Manual
T0SE
3
PSA
1
0
PS
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the PICmicro™ Mid-Range Reference
Manual, (DS33023).
5.2
An 8-bit counter is available as a prescaler for the Timer0
module, or as a postscaler for the Watchdog Timer,
respectively (Figure 5-2). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet. Note that there is only one prescaler available
which is mutually exclusively shared between the Timer0
module and the Watchdog Timer. Thus, a prescaler
assignment for the Timer0 module means that there is no
prescaler for the Watchdog Timer, and vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watchdog
Timer (WDT). When the prescaler is assigned to the
WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,etc.) will clear the prescaler. When assigned to
WDT, a CLRWDT instruction will clear the prescaler
along with the WDT.
Note:
OUT
(2 Cycle Delay)
Sync with
Prescaler
Internal
Clocks
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
OSC
). Also, there is a delay in the actual
PS
OUT
PIC16F84A
Data Bus
TMR0
8
DS35007B-page 19
Flag bit T0IF
Set Interrupt
on Overflow