PIC16F84A-04I/P Microchip Technology Inc., PIC16F84A-04I/P Datasheet - Page 30

• Manufacturer Part Number: PIC16F84A-04I/P
• Description: 18 PIN, 1.75 KB FLASH, 68 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F84A-04I/P

• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 68 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F84A
FIGURE 6-9:
6.7
On power-up (Figures 6-6 through 6-9), the time-out
sequence is as follows:
1.
2.
The total time-out will vary based on oscillator configu-
ration and PWRTE configuration bit status. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
TABLE 6-5:
DS35007B-page 28
Configuration
XT, HS, LP
Oscillator
INTERNAL RESET
PWRT time-out is invoked after a POR has
expired.
Then, the OST is activated.
PWRT TIME-OUT
INTERNAL POR
OST TIME-OUT
RC
Time-out Sequence and
Power-down Status Bits (TO/PD)
When V
has reached its final value. In this example, the chip will reset properly if, and only if, V1
MCLR
V
1024T
TIME-OUT IN VARIOUS
SITUATIONS
DD
Enabled
72 ms +
PWRT
DD
72 ms
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
SLOW V
rises very slowly, it is possible that the T
Power-up
OSC
1024T
Disabled
PWRT
DD
—
RISE TIME
OSC
1024T
Wake-up
SLEEP
from
—
OSC
PWRT
T
PWRT
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high, execution will begin immediately
(Figure 6-6). This is useful for testing purposes or to
synchronize more than one PIC16F84A device when
operating in parallel.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the RESET conditions for some special
registers, while Table 6-4 lists the RESET conditions
for all the registers.
TABLE 6-6:
time-out and T
TO
1
0
x
0
0
1
1
PD
1
x
0
1
0
1
0
OST
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset (during normal operation)
WDT Wake-up
MCLR during normal operation
MCLR during SLEEP or interrupt
wake-up from SLEEP
time-out will expire before V
STATUS BITS AND THEIR
SIGNIFICANCE
T
OST
V1
2001 Microchip Technology Inc.
DD
Condition
V
):
DD
min.
DD