PIC16F1827-I/SS Microchip Technology Inc., PIC16F1827-I/SS Datasheet - Page 206

• Manufacturer Part Number: PIC16F1827-I/SS
• Description: 20 SSOP .209in TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-I/SS

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SSOP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16(L)F1826/27
24.2
The Compare mode function described in this section
is available and identical for CCP modules ECCP1,
ECCP2, CCP3 and CCP4.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
All Compare modes can generate an interrupt.
Figure 24-2
Compare operation.
FIGURE 24-2:
24.2.1
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Also, the CCPx pin function can be moved to
alternative pins using the APFCON0 register. Refer to
Section 12.1 “Alternate Pin Function”
details.
DS41391D-page 206
Note:
CCPx
Pin
Output Enable
TRIS
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
shows a simplified diagram of the
Q
Special Event Trigger
CCPxM<3:0>
R
S
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
Set CCPxIF Interrupt Flag
4
(PIRx)
Match
CCPRxH CCPRxL
TMR1H
Comparator
for more
TMR1L
24.2.2
In Compare mode, Timer1 must be running in either Timer
mode or Synchronized Counter mode. The compare
operation may not work in Asynchronous Counter mode.
See
for more information on configuring Timer1.
24.2.3
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
24.2.4
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCPx module does not assert control of the CCPx
pin in this mode.
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. The
Special Event Trigger output starts an A/D conversion
(if the A/D module is enabled). This allows the
CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1.
TABLE 24-3:
Refer to
more information.
Note:
Note 1: The Special Event Trigger from the CCP
Section 21.0 “Timer1 Module with Gate Control”
PIC16(L)F1826
PIC16(L)F1827
2: Removing
Section 16.2.5 “Special Event Trigger”
Device
TIMER1 MODE RESOURCE
Clocking Timer1 from the system clock
(F
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (F
external clock source.
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates
preclude the Reset from occurring.
OSC
) should not be used in Compare
SPECIAL EVENT TRIGGER
 2011 Microchip Technology Inc.
the
the
match
Timer1
OSC
CCPx/ECCPx
/4) or from an
ECCP1
CCP4
condition
Reset,
will
by
for