PIC16F1827-I/SS Microchip Technology Inc., PIC16F1827-I/SS Datasheet - Page 310

• Manufacturer Part Number: PIC16F1827-I/SS
• Description: 20 SSOP .209in TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-I/SS

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SSOP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16(L)F1826/27
FIGURE 26-12:
TABLE 26-8:
DS41391D-page 310
APFCON0
APFCON1
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TRISB
TXSTA
Legend:
Note 1:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
SREN bit
CREN bit
bit SREN
RCIF bit
Name
RCREG
RX/DT
Write to
Read
pin
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
Page provides register information.
PIC16(L)F1827 only.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
RXDTSEL
TMR1GIE
TMR1GIF
ABDOVF
TRISB7
SPEN
CSRC
Bit 7
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
—
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
SDO1SEL
TRISB6
RCIDL
bit 0
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
—
bit 1
SS1SEL
TMR0IE
TRISB5
SREN
TXEN
RCIE
RCIF
Bit 5
—
—
EUSART Receive Data Register
bit 2
P2BSEL
TRISB4
CREN
SYNC
SCKP
Bit 4
INTE
TXIE
TXIF
—
BRG<15:8>
BRG<7:0>
(1)
bit 3
CCP2SEL
ADDEN
TRISB3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
Bit 3
—
bit 4
(1)
P1DSEL
TMR0IF
CCP1IE
CCP1IF
TRISB2
BRGH
FERR
Bit 2
—
—
bit 5
P1CSEL
TMR2IE
TMR2IF
TRISB1
OERR
TRMT
WUE
Bit 1
INTF
 2011 Microchip Technology Inc.
bit 6
—
CCP1SEL
TXCKSEL
TMR1IE
TMR1IF
TRISB0
ABDEN
bit 7
IOCIF
RX9D
TX9D
Bit 0
Register
on Page
290*
297*
297*
119
119
296
295
127
294
86
87
91
‘0’