PIC16F870-I/SP Microchip Technology Inc., PIC16F870-I/SP Datasheet - Page 17

• Manufacturer Part Number: PIC16F870-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F870-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 2-1:
 2003 Microchip Technology Inc.
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
Legend:
Note 1:
Address
Bank 2
Bank 3
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(1,4)
(4)
(1,4)
(4)
2:
3:
4:
5:
INDF
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
INDF
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
Name
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
Program Counter's (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
EEPROM Data Register
EEPROM Address Register
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
EEPROM Control Register2 (not a physical register)
Reserved maintain clear
Reserved maintain clear
EEPGD
RBPU
Bit 7
IRP
GIE
IRP
GIE
—
—
—
—
INTEDG
Bit 6
PEIE
PEIE
RP1
RP1
—
—
—
—
—
EEPROM Data Register High Byte
T0CS
Bit 5
T0IE
T0IE
RP0
RP0
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
EEPROM Address Register High Byte
Write Buffer for the upper 5 bits of the Program Counter
Bit 4
T0SE
INTE
INTE
TO
TO
—
WRERR
Bit 3
RBIE
RBIE
PSA
PD
PD
WREN
Bit 2
T0IF
T0IF
PS2
Z
Z
PIC16F870/871
Bit 1
INTF
INTF
PS1
WR
DC
DC
Bit 0
RBIF
RBIF
PS0
RD
C
C
POR, BOR
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 0000 ---0 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---0 0000 ---0 0000
0000 000x 0000 000u
x--- x000 x--- u000
---- ---- ---- ----
0000 0000 0000 0000
0000 0000 0000 0000
Value on:
DS30569B-page 15
—
—
—
—
—
—
—
—
RESETS
Value on
all other
—
—
—
—
—
—
—
—
(2)