PIC16F76-I/SS Microchip Technology Inc., PIC16F76-I/SS Datasheet - Page 45

• Manufacturer Part Number: PIC16F76-I/SS
• Description: 28 PIN, 14 KB FLASH, 368 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F76-I/SS

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SSOP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family Refer-
ence Manual (DS33023).
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Timer0
OPTION_REG register (Register 5-1 on the following
page). Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
 2002 Microchip Technology Inc.
RA4/T0CKI
CLKOUT (= F
WDT Enable bit
pin
Watchdog
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
Timer
TIMER0 MODULE
operation
OSC
/4)
T0SE
is
BLOCK DIAGRAM OF THE TIMER0 MODULE AND PRESCALER
controlled
0
1
PSA
M
U
X
0
1
T0CS
M
through
U
X
0
8-bit Prescaler
8 - to - 1MUX
Time-out
8
M U X
WDT
the
PRESCALER
1
0
1
PSA
M
U
X
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
5.1
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine, before re-enabling this inter-
rupt. The TMR0 interrupt cannot awaken the processor
from SLEEP, since the timer is shut-off during SLEEP.
PSA
Timer0
PS2:PS0
Timer0 Interrupt
Cycles
SYNC
2
Source
Edge
TMR0 reg
Data Bus
PIC16F7X
8
Select
Set Flag bit TMR0IF
DS30325B-page 43
on Overflow
bit
T0SE