PIC16F76-I/SS Microchip Technology Inc., PIC16F76-I/SS Datasheet - Page 50

• Manufacturer Part Number: PIC16F76-I/SS
• Description: 28 PIN, 14 KB FLASH, 368 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F76-I/SS

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SSOP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X
6.1
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>) has no effect, since the internal clock is
always in sync.
FIGURE 6-1:
6.3
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
FIGURE 6-2:
DS30325B-page 48
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
Timer1 Operation in Timer Mode
Timer1 Operation in Synchronized
Counter Mode
OSC
/4. The synchronize control bit T1SYNC
2: For the PIC16F73/76, the Schmitt Trigger is not implemented in External Clock mode.
Set Flag bit
TMR1IF on
Overflow
TIMER1 INCREMENTING EDGE
TIMER1 BLOCK DIAGRAM
(2)
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
Enable
T1OSCEN
(1)
(2)
Clock
Internal
F
OSC
/4
TMR1ON
6.2
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
On/Off
TMR1CS
1
0
Timer1 Counter Operation
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
 2002 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
Q Clock
det