PIC24FJ64GA002-I/SO Microchip Technology Inc., PIC24FJ64GA002-I/SO Datasheet
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PIC24FJ64GA002-I/SO Summary of contents
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... PIC24FJ64GA004 Family © 2007 Microchip Technology Inc. Data Sheet 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers Preliminary DS39881B ...
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... EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , K L logo, microID, MPLAB, PIC DSCs ® code hopping devices, Serial EE OQ © 2007 Microchip Technology Inc. ® ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Analog Features: • 10-Bit 13-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/Output Configuration Peripheral Features: • Peripheral Pin Select: ...
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... REF 4 25 AN11/RP13/CN13/PMRD/RB13 5 24 AN12/RP12/CN14/PMD0/RB12 6 23 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 7 22 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 CAP DDCORE DISVREG 10 19 TDO/RP9/SDA1/CN21/PMD3/RB9 11 18 TCK/RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGC3/EMUC3/RP6/SCL1 /CN27/x/RB5 AN11/RP13/CN13/PMRD/RB13 2 20 AN12/RP12/CN14/PMD0/RB12 3 19 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 PIC24FJXXGA002 4 18 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 CAP DDCORE 6 16 DISVREG 7 15 TDO/RP9/SDA1/CN21/PMD3/RB9 Preliminary /RTCC/RP14/CN12/PMWR/RB14 (2) /CN24/PMD6/RB6 © 2007 Microchip Technology Inc. ...
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... PWM, comparator digital outputs and SPI. For more information, see Section 9.4 “Peripheral Pin Select” and the specific peripheral sections. 2: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY SOSCI/RP4/CN1/RB4 33 ...
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... Select” and the specific peripheral sections. 2: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared. DS39881B-page 4 33 SOSCI/RP4/CN1/RB4 1 32 TDO/PMA8/RA8 2 31 OSCO/CLKO/CN29/RA3 3 30 OSCI/CLKI/CN30/RA2 PIC24FJXXGA004 AN8/RP18/CN10/PMA2/RC2 7 26 AN7/RP17/CN9/RC1 8 AN6/RP16/CN8/RC0 25 9 AN5/C1IN+/RP3/SCL2/CN7/RB3 24 10 AN4/C1IN-/RP2/SDA2/CN6/RB2 23 11 Preliminary © 2007 Microchip Technology Inc. ...
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... Electrical Characteristics .......................................................................................................................................................... 223 27.0 Packaging Information.............................................................................................................................................................. 237 Appendix A: Revision History............................................................................................................................................................. 245 Index ................................................................................................................................................................................................. 247 The Microchip Web Site ..................................................................................................................................................................... 251 Customer Change Notification Service .............................................................................................................................................. 251 Customer Support .............................................................................................................................................................................. 251 Reader Response .............................................................................................................................................................................. 252 Product Identification System ............................................................................................................................................................ 253 © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39881B-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ16GA002 • PIC24FJ32GA002 • PIC24FJ48GA002 • PIC24FJ64GA002 • PIC24FJ16GA004 • PIC24FJ32GA004 • PIC24FJ48GA004 • PIC24FJ64GA004 This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance ...
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... Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary memory (64 Kbytes for devices, 48 Kbytes for devices, 32 Kbytes for features available on the © 2007 Microchip Technology Inc. ...
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... JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Remappable Pins Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY DC – 32 MHz 16K 32K 48K 64K 5,504 11,008 16,512 ...
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... Divide Control Signals Support Reg Array 17x17 Multiplier (2) MCLR 10-Bit (3) (3) RTCC Timer4/5 ADC (3) (1) SPI1/2 I2C1/2 CN1-22 (3) Preliminary 16 (1) PORTA RA0:RA9 16 16 PORTB RB0:RB15 16 (1) PORTC 16 RC0:RC9 (1) RP RP0:RP25 16-Bit ALU 16 (3) Comparators PMP/PSP (3) UART1/2 © 2007 Microchip Technology Inc. ...
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... CLKI 9 6 CLKO 10 7 Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Input I/O 44-Pin Buffer 19 I ANA A/D Analog Inputs. 20 ...
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... In-Circuit Emulator Data Input/Output. 42 I/O ST In-Circuit Emulator Clock Input/Output. 41 I/O ST In-Circuit Emulator Data Input/Output External Interrupt Input Master Clear (device Reset) Input. This line is brought low to cause a Reset Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2007 Microchip Technology Inc. ...
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... PMWR 25 22 Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Input I/O 44-Pin Buffer 30 I ANA Main Oscillator Input Connection. ...
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... PORTA Digital I/ I/O ST PORTB Digital I/ I/O ST PORTC Digital I/ Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2007 Microchip Technology Inc. ...
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... SOSCI 11 8 SOSCO 12 9 Legend: TTL = TTL input buffer ANA = Analog level input/output Note 1: Alternative multiplexing for SDA1 and SCL1 when I2C1SEL Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Input I/O 44-Pin Buffer 21 I/O ST Remappable Peripheral. 22 I/O ST ...
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... Positive Supply for Microcontroller Core Logic (regulator disabled ANA A/D and Comparator Reference Voltage (low) Input ANA A/D and Comparator Reference Voltage (high) Input. 29 — Ground Reference for Logic and I/O Pins Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2007 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Various Blocks DS39881B-page 18 Data Bus 16 16 Data Latch PCH PCL Data RAM Address Loop Latch Control Logic RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support Preliminary 16-Bit ALU 16 To Peripheral Modules © 2007 Microchip Technology Inc. ...
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... W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register ...
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... Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39881B-page 20 U-0 U-0 — — (1) R-0 R/W-0 ( Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. Description Preliminary © 2007 Microchip Technology Inc. ...
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... Device Config Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”. ...
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... PIC24FJ64GA least significant word Instruction Width Preliminary FLASH CONFIGURATION WORDS FOR PIC24FJ64GA004 FAMILY DEVICES Program Configuration Memory Word (K words) Addresses 002BFCh: 5.5 002BFEh 0057FCh: 11 0057FEh 0083FCh: 16 0083FEh 00ABFCh: 22 00ABFEh PC Address (lsw Address) 0 000000h 000002h 000004h 000006h © 2007 Microchip Technology Inc. ...
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... Note 1: Data memory areas are not shown to scale. 2: Upper memory limit for PIC24FJ16GAXXX devices is 17FFh. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PIC24FJ64GA family devices implement a total of 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned ...
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... CRC — System NVM/PMD — Preliminary xxA0 xxC0 xxE0 Interrupts — — — — — I/O — — — — — — — — — PPS — — — © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 27 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 28 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 29 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 30 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 31 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 32 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 33 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 34 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 35 ...
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... PIC24FJ64GA004 FAMILY DS39881B-page 36 Preliminary © 2007 Microchip Technology Inc. ...
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... W15 (before CALL) 000000000 PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 3.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Select 1 PSVPAG 0 8 bits 23 bits Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 bits bits Byte Select © 2007 Microchip Technology Inc. ...
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... FIGURE 3-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the “phantom byte”, will always be ‘0’. ...
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... PSV Area 800000h Preliminary 1111’ or 0000h Data EA<14:0> 8000h ...while the lower 15 bits of the EA specify an exact address within the PSV area. FFFFh This corresponds exactly to the same lower 15 bits of the actual program space address. © 2007 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- tions (192 bytes time, and erase program memory in blocks of 512 instructions (1536 bytes time ...
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... Configuration Word values are stored in the last two locations of program memory. Performing a page erase operation on the last page of program memory clears these values and enables code protection result, avoid performing page erase operations on the last page of program memory. Preliminary © 2007 Microchip Technology Inc. ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP3:NVMOP0 are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY (1) U-0 U-0 — — ...
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... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2007 Microchip Technology Inc. ...
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... W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR BTSC NVMCON, #15 BRA $-2 © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; ; Set NVMOP bits to 0011 ; Disable interrupts while the KEY sequence is written ; Write the key sequence ; Start the write cycle Preliminary © 2007 Microchip Technology Inc. ...
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... DD Brown-out Reset Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized W Register © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A Power-on Reset will clear all bits except for the BOR and POR bits (RCON< ...
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... SWDTEN bit setting. DS39881B-page 48 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Setting Event 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... OST LOCK T — RST T — RST T — RST T — RST T — RST T — RST PWRT Preliminary FSCM Notes Delay — FSCM FSCM FSCM — FSCM FSCM FSCM — 3 — 3 — 3 — 3 — 3 — 3 (64 ms nominal) if on-chip © 2007 Microchip Technology Inc. ...
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... FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 5.2.2.1 FSCM Delay for Crystal and PLL ...
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... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 52 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC24FJ64GA004 family devices non-maskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
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... Alternate Interrupt Vector Table (AIVT) — 00017Ch 00017Eh 000180h — — — 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 0001172h Reserved Preliminary (1) (1) Trap Source © 2007 Microchip Technology Inc. ...
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... SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter LVD Low-Voltage Detect © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Vector AIVT IVT Address Number Address 13 00002Eh 00012Eh 18 000038h 000138h 67 ...
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... IPL2:IPL0, also indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All interrupt registers are described in Register 6-1 through Register 6-29, in the following pages. Preliminary © 2007 Microchip Technology Inc. ...
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... Note 1: See Register 2-2 for the description of remaining bit (s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS39881B-page 58 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt request has not occurred DS39881B-page 60 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPF1IF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF ...
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... Interrupt request has not occurred DS39881B-page 62 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 U-0 OC5IF — bit 8 R/W-0 R/W-0 SPI2IF SPF2IF bit Bit is unknown ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS39881B-page 64 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 R/W-0 — LVDIF bit 8 R/W-0 U-0 U1ERIF — bit Bit is unknown ...
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... Interrupt request enabled 0 = Interrupt request not enabled Note 1: If INTxIE = 1, this external interrupt input must be configured to an available RPx pin. See Section 9.4 ”Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE ...
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... DS39881B-page 66 R/W-0 R/W-0 R/W-0 (1) T5IE T4IE OC4IE R/W-0 R/W-0 R/W-0 (1) INT1IE CNIE CMIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 U-0 OC3IE — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS39881B-page 68 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 SI2C2IE — bit Bit is unknown ...
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... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Interrupt source is disabled DS39881B-page 70 R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 U-0 R/W-1 IC1IP0 — INT0IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP1 OC1IP0 bit 8 R/W-0 R/W-0 INT0IP1 INT0IP0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 ...
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... Interrupt source is disabled DS39881B-page 72 R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 U-0 R/W-1 SPF1IP0 — T3IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP1 SPI1IP0 bit 8 R/W-0 R/W-0 T3IP1 T3IP0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
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... Interrupt source is disabled DS39881B-page 74 R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 U-0 R/W-1 MI2C1P0 — SI2C1P2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CMIP1 CMIP0 bit 8 R/W-0 R/W-0 SI2C1P1 SI2C1P0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Unimplemented: Read as ‘0’ DS39881B-page 76 R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 U-0 U-0 OC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC4IP1 OC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 ...
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... Interrupt source is disabled DS39881B-page 78 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 SPI2IP0 — SPF2IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SPF2IP1 SPF2IP0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 ...
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... Unimplemented: Read as ‘0’ DS39881B-page 82 U-0 U-0 R/W-1 — — RTCIP2 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 RTCIP1 RTCIP0 bit 8 U-0 U-0 — — bit Bit is unknown ...
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... U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 ...
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... Interrupt source is disabled DS39881B-page 84 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — — LVDIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 LVDIP1 LVDIP0 bit Bit is unknown ...
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... ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 88
... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 86 Preliminary © 2007 Microchip Technology Inc. ...
Page 89
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes • On-chip 4x PLL to boost internal operating frequency on select internal and external oscillator sources • ...
Page 90
... Primary 10 Primary 01 Primary 00 Internal 00 Internal 00 Preliminary the program memory (refer to “Configuration Bits” for further (Configuration Word 2<10:8>), Configuration bits (Configuration FNOSC2: Note FNOSC0 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 © 2007 Microchip Technology Inc. ...
Page 91
... The OSCCON register (Register 7-1) is the main con- trol register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY The Clock Divider register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator ...
Page 92
... U-0 COSC0 — (3) U-0 R/CO-0 — Set-Only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) Preliminary (1) (1) (1) R/W-x R/W-x R/W-x NOSC2 NOSC1 NOSC0 bit 8 U-0 R/W-0 R/W-0 — SOSCEN OSWEN bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 93
... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 91 ...
Page 94
... This bit is automatically cleared when the ROI bit is set and an interrupt occurs. DS39881B-page 92 R/W-0 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-1 RCDIV1 RCDIV0 bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 95
... HS and EC) which are determined by the POSCMDx Configuration bits. While an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
Page 96
... MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 Preliminary 9Ah to in two back-to-back 46h and 57h to © 2007 Microchip Technology Inc. ...
Page 97
... Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes said to “ ...
Page 98
... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows fur- ther reduction of power consumption during Idle mode, possible enhancing power savings for extremely critical power applications. Preliminary © 2007 Microchip Technology Inc. ...
Page 99
... CK WR PORT Data Latch Read LAT Read PORT © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 100
... DDCORE there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Preliminary © 2007 Microchip Technology Inc. ...
Page 101
... I C™, change notification inputs, RTCC alarm outputs or peripherals with analog inputs. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A key difference between pin select and non pin select peripherals is that pin select peripherals are not asso- ciated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used ...
Page 102
... This permits any given pin to remain discon- nected from the output of any of the pin selectable peripherals. Preliminary (1) Configuration Bits INTR1<4:0> INTR2R<4:0> T2CKR<4:0> T3CKR<4:0> T4CKR<4:0> T5CKR<4:0> IC1R<4:0> IC2R<4:0> IC3R<4:0> IC4R<4:0> IC5R<4:0> OCFAR<4:0> OCFBR<4:0> U1RXR<4:0> U1CTSR<4:0> U2RXR<4:0> U2CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0> © 2007 Microchip Technology Inc. ...
Page 103
... PIC24F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 9.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed ...
Page 104
... Assign U1TX To Pin RP2 //*************************** RPOR1bits.RP2R = 3; //*************************** // Assign U1RTS To Pin RP3 //*************************** RPOR1bits.RP3R = 4; //************************************* // Lock Registers //************************************* asm volatile ( "MOV "MOV "MOV "MOV.b "MOV.b "BSET Preliminary © 2007 Microchip Technology Inc. #OSCCON, w1 \n" #0x46, w2 \n" #0x57, w3 \n" w2, <w1> \n" w3, <w1> \n" #OSCCON, w1 \n" #0x46, w2 \n" #0x57, w3 \n" ...
Page 105
... Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 INTR2R4:INTR2R0: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Note: Input and output register values can only be changed if OSCCON<IOLOCK> See Section 9.4.4.1 “Control Register Lock” ...
Page 106
... T4CKR3 T4CKR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 T3CKR1 T3CKR0 bit 8 R/W-1 R/W-1 T2CKR1 T2CKR0 bit Bit is unknown R/W-1 R/W-1 T5CKR1 T5CKR0 bit 8 R/W-1 R/W-1 T4CKR1 T4CKR0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 107
... IC4R4:IC4R0: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 IC3R4:IC3R0: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 IC2R4 ...
Page 108
... OCFAR3 OCFAR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-1 R/W-1 IC5R1 IC5R0 bit Bit is unknown R/W-1 R/W-1 OCFBR1 OCFBR0 bit 8 R/W-1 R/W-1 OCFAR1 OCFAR0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 109
... U2CTSR4:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to the Corresponding RPn Pin bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 U2RXR4:U2RXR0: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 ...
Page 110
... SS1R3 SS1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 SCK1R1 SCK1R0 bit 8 R/W-1 R/W-1 SDI1R1 SDI1R0 bit Bit is unknown U-0 U-0 — — bit 8 R/W-1 R/W-1 SS1R1 SS1R0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 111
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS2R4:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn Pin bits © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 ...
Page 112
... RP2R3 RP2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP1R1 RP1R0 bit 8 R/W-0 R/W-0 RP0R1 RP0R0 bit Bit is unknown R/W-0 R/W-0 RP3R1 RP3R0 bit 8 R/W-0 R/W-0 RP2R1 RP2R0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 113
... RP7R4:RP7R0: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R4:RP6R0: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP5R4 RP5R3 ...
Page 114
... RP10R3 RP10R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP9R1 RP9R0 bit 8 R/W-0 R/W-0 RP8R1 RP8R0 bit Bit is unknown R/W-0 R/W-0 RP11R1 RP11R0 bit 8 R/W-0 R/W-0 RP10R1 RP10R0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 115
... RP15R4:RP15R0: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R4:RP14R0: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP13R4 RP13R3 ...
Page 116
... RP18R3 RP18R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP17R1 RP17R0 bit 8 R/W-0 R/W-0 RP16R1 RP16R0 bit Bit is unknown R/W-0 R/W-0 RP19R1 RP19R0 bit 8 R/W-0 R/W-0 RP18R1 RP18R0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 117
... RP23R4:RP23R0: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP22R4:RP22R0: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 RP21R4 RP21R3 ...
Page 118
... DS39881B-page 116 R/W-0 R/W-0 R/W-0 RP25R4 RP25R3 RP25R2 R/W-0 R/W-0 R/W-0 RP24R4 RP24R3 RP24R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP25R1 RP25R0 bit 8 R/W-0 R/W-0 RP24R1 RP24R0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 119
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 120
... DS39881B-page 118 U-0 U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...
Page 122
... Pin Select” for more information. 3: The ADC Event Trigger is available only on Timer4/5. DS39881B-page 120 Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR3 TMR2 (TMR5) (TMR4) 16 (1) ( TMR3H (TMR5H) Preliminary TCKPS1:TCKPS0 2 TON 1x Prescaler 1, 8, 64, 256 01 00 (2) TGATE (2) TCS Sync © 2007 Microchip Technology Inc. ...
Page 123
... Equal Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. 2: The ADC Event Trigger is available only on Timer4/5. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 1x Gate Sync 01 ...
Page 124
... U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) OSC Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 125
... When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 (1) — ...
Page 126
... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 124 Preliminary © 2007 Microchip Technology Inc. ...
Page 127
... An ‘x’ signal, register or bit name denotes the number of the capture channel. 2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY comprehensive FIFO ...
Page 128
... DS39881B-page 126 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE ICM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM1 ICM0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 129
... OCxIE bit. For further information on peripheral interrupts, refer to Section 6.0 “Interrupt Controller”. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 10. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘ ...
Page 130
... Table 13-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F • (Timer Prescale Value) PWM log ( /2; Doze mode and PLL are disabled Preliminary CALCULATING THE PWM (1) PERIOD • (Timer Prescale Value /2; Doze mode and CY CY (1) ) bits © 2007 Microchip Technology Inc. ...
Page 131
... EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Note 1: Based /2; Doze mode and PLL are disabled © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • (Timer 2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 122 Hz 977 ...
Page 132
... This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” section for more information. DS39881B-page 130 Set Flag bit (1) OCxIF Output S Q Logic R Output Enable 3 OCM2:OCM0 Mode Select 0 1 Period match signals from time bases (see Note 3). Preliminary (1) OCx (2) OCFA or OCFB © 2007 Microchip Technology Inc. ...
Page 133
... Note 1: RPORx (OCx) must be configured to an available RPn pin. For more information, see Section 9.4 “Peripheral Pin Select”. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...
Page 134
... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 132 Preliminary © 2007 Microchip Technology Inc. ...
Page 135
... SPIx or separately as SPI1 and SPI2. Special Function Reg- isters will follow a similar notation. For example, SPIxCON refers to the control register for the SPI1 or SPI2 module. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY To set up the SPI module for the Standard Master mode of operation: 1. ...
Page 136
... SPIBEN bit (SPIxCON2<0>). 8. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPIxBUF 16 Internal Data Bus Preliminary registers with MSTEN 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2007 Microchip Technology Inc. ...
Page 137
... Sync Control Control Clock SDOx bit0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer 8-Level FIFO Transmit Buffer Write SPIxBUF 16 Internal Data Bus ...
Page 138
... DS39881B-page 136 U-0 U-0 — — SPIBEC2 R/W-0 R/W-0 R/W-0 SISEL2 SISEL1 SISEL0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-0 R-0 R-0 SPIBEC1 SPIBEC0 bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 139
... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 137 ...
Page 140
... R/W-0 R/W-0 (1) (2) DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) Preliminary R/W-0 R/W-0 (3) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 141
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — ...
Page 142
... SDIx SDOx Serial Clock SCKx SCKx SSx SSx SSEN (SPIxCON1<7> MSTEN (SPIxCON1<5> and SPIBEN (SPIxCON2<0> Preliminary (SPIxRXB) Shift Register (SPIxSR) LSb (SPIxTXB) SPIx Buffer (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-level FIFO Buffer SPIx Buffer (SPIxBUF) © 2007 Microchip Technology Inc. ...
Page 143
... FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave) © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...
Page 144
... Preliminary (1) 4:1 6:1 8:1 4000 2667 2000 1000 667 500 250 167 125 1250 833 625 313 208 156 © 2007 Microchip Technology Inc. ...
Page 145
... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 15-1. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 15.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 146
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007 Microchip Technology Inc. ...
Page 147
... C™ definition, the addresses in Table 15-2 on page 146 are reserved and will not be 2 acknowledged by the I C peripheral operating in Slave mode. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY module to respond whether the corresponding address bit value is a ‘0’ ‘1’. For example, when I2CxMSK is set to ‘ ...
Page 148
... The above address bits will never cause an address match, independent of address mask settings. 2: Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. DS39881B-page 146 (1) Description (2) (3) Preliminary © 2007 Microchip Technology Inc. ...
Page 149
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enables software or receive clock stretching 0 = Disables software or receive clock stretching © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 150
... Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS39881B-page 148 2 C master. Applicable during master receive master. Applicable during master 2 C master Hardware clear at end of eighth bit of master receive data byte master master master) Preliminary © 2007 Microchip Technology Inc. ...
Page 151
... D/A: Data/Address bit (when operating Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by write to I2CxTRN or by reception of slave byte. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/C-0, HS — ...
Page 152
... Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS39881B-page 150 2 C slave device address byte. Preliminary © 2007 Microchip Technology Inc. ...
Page 153
... AMSK9:AMSK0: Mask for Address Bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...
Page 154
... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 152 Preliminary © 2007 Microchip Technology Inc. ...
Page 155
... Note: This peripheral’s inputs and outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY • One or Two Stop bits • Hardware Flow Control Option with UxCTS and UxRTS Pins • ...
Page 156
... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. Preliminary /(16 * 65536). UART BAUD RATE WITH (1,2) BRGH = • (UxBRG + – • Baud Rate denotes the instruction cycle clock = T /2; Doze mode and (1) © 2007 Microchip Technology Inc. ...
Page 157
... Write ‘55h’ to UxTXREG – loads Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
Page 158
... IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) Preliminary (3) (3) R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 159
... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 2: This feature is only available for the 16x BRG mode (BRGH = 0). 3: Bit availability depends on pin availability. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 157 ...
Page 160
... R/W-0 — UTXBRK UTXEN R-1 R-0 R-0 RIDLE PERR FERR HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R-0 R-1 (2) UTXBF TRMT bit 8 R/C-0 R-0 OERR URXDA bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 161
... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1 UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 159 ...
Page 162
... URX3 URX2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-x W-x — UTX8 bit 8 W-x W-x UTX1 UTX0 bit Bit is unknown U-0 R-0 — URX8 bit 8 R-0 R-0 URX1 URX0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 163
... PMP MODULE OVERVIEW PIC24F Parallel Master Port (1) Note 1: Devices with 28 pins do not have PMA<10:2>. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Key features of the PMP module include: • Programmable Address Lines • One Chip Select Line • Programmable Strobe Options - Individual Read and Write Strobes or; ...
Page 164
... R/W-0 R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN (1) (1) U-0 R/W-0 R/W-0 — CS1P U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) Preliminary R/W-0 R/W-0 PTWREN PTRDEN bit 8 R/W-0 R/W-0 BEP WRSP RDSP bit Bit is unknown (1) © 2007 Microchip Technology Inc. ...
Page 165
... For Master mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: Devices with 28 pins do not have PMA<10:2>. 2: These bits have no effect when their corresponding pins are used as address lines. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 163 ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ; multiplexed address phase multiplexed address phase multiplexed address phase multiplexed address phase Preliminary R/W-0 R/W-0 R/W-0 MODE1 MODE0 bit 8 R/W-0 R/W-0 R/W-0 (1) (1) WAITE1 WAITE0 bit Bit is unknown ( (1) © 2007 Microchip Technology Inc. ...
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... PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O Note 1: Devices with 28 pins do not have PMA<10:2>. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-0 — ...
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... DS39881B-page 166 U-0 R-0 R-0 — IB3F IB2F U-0 R-1 R-1 — OB3E OB2E U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R-0 R-0 IB1F IB0F bit 8 R-1 R-1 OB1E OB0E bit Bit is unknown ...
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... PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — ...
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... PMDOUT1<7:0> (0) PMDOUT1<15:8> (1) PMDOUT2<7:0> (2) PMDOUT2<15:8> (3) PMA<10:0> PMD<7:0> PMCS1 PMRD PMWR Preliminary Address Bus Data Bus Control Lines Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) Input Register (Buffer) PMDIN1<7:0> (0) PMDIN1<15:8> (1) PMDIN2<7:0> (2) PMDIN2<15:8> (3) Address Bus Data Bus Control Lines © 2007 Microchip Technology Inc. ...
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... PMD<7:0> PMALL PMALH PMCS1 PMRD PMWR FIGURE 17-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<10:8> PMCS1 PMRD PMWR © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PMA<10:8> PMD<7:0> PMA<7:0> PMCS1 PMALL PMRD PMWR PMD<7:0> PMA<7:0> PMA<15:8> PMCS1 PMALL PMALH ...
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... Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> LCD Controller D<7:0> RS R/W E Preliminary Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2007 Microchip Technology Inc. ...
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... RTCC Clock Domain 32.768 kHz Input from SOSC Oscillator RTCC Prescalers RTCC Timer Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY CPU Clock Domain RCFGCAL ALCFGRPT 0.5s RTCVAL ALRMVAL RTCC Interrupt Logic Preliminary YEAR ...
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... Example 18-1. ;move the address of NVMKEY into W1 ;start 55/AA sequence ;set the RTCWREN bit Preliminary ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN ALRMSEC ALRMWD ALRMHR ALRMMNTH ALRMDAY — — © 2007 Microchip Technology Inc. ...
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... Note 1: The RCFGCAL register is only affected by a POR write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R-0 R-0 R/W-0 (3) RTCSYNC ...
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... DS39881B-page 174 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary © 2007 Microchip Technology Inc. (1) (CONTINUED) U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) RTSECSEL PMPTTL bit Bit is unknown ...
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... ARPT7:ARPT0: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 ...
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... DAYONE3 DAYONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-x R/W-x YRONE1 YRONE0 bit Bit is unknown R-x R-x MTHONE1 MTHONE0 bit 8 R/W-x R/W-x DAYONE1 DAYONE0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 R/W-x — ...
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... HRONE3 HRONE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-x R/W-x MTHONE1 MTHONE0 bit 8 R/W-x R/W-x DAYONE1 DAYONE0 bit Bit is unknown (1) R/W-x R/W-x WDAY1 WDAY0 bit 8 R/W-x R/W-x HRONE1 HRONE0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Once the error is known, it must be converted to the number of error clock pulses per minute. EQUATION 18-1: (Ideal Frequency† – Measured Frequency Clocks per Minute † Ideal frequency = 32,768 Hz © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-x R/W-x R/W-x MINTEN0 MINONE3 MINONE2 ...
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... To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0 recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. Day of the Week Month Day Hours Preliminary Minutes Seconds © 2007 Microchip Technology Inc. ...
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... Start CRC serial shifter 0 = CRC serial shifter turned off bit 3-0 PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY 19.1 Registers There are four registers used to control programmable CRC operation: • ...
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... Unimplemented: Read as ‘0’ DS39881B-page 182 R/W-0 R/W-0 R/W-0 X12 X11 X10 R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared n Enable bits Preliminary R/W-0 R/W bit 8 R/W-0 U-0 X1 — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... OUT IN BIT 0 D OUT 1 p_clk © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY TABLE 19-1: Bit Name PLEN3:PLEN0 X<15:1> Note that for the value of X<15:1>, the 12th bit and the 5th bit are set to ‘1’, as required by the equation. The 0th bit required by the equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed ...
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... If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. Preliminary BIT 12 BIT 15 p_clk p_clk CRC Read Bus CRC Write Bus © 2007 Microchip Technology Inc. ...
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... The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY A block diagram of the A/D Converter is shown in Figure 20-1. ...
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... S/H DAC V INL 10-Bit SAR Data Formatting AD1BUF0: AD1BUFF AD1CON1 AD1CON2 AD1CON3 INH AD1CHS0 AD1PCFG AD1CSSL INL Sample Control Control Logic Input MUX Control Pin Config. Control Preliminary (1) Internal Data Bus 16 Comparator + R Conversion Logic Conversion Control © 2007 Microchip Technology Inc. ...
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... SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY U-0 U-0 U-0 — — — ...
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... SMPI0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared External V + pin AV REF AV External V DD External V + pin External V REF Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 BUFM ALTS bit Bit is unknown - pin REF - pin REF SS © 2007 Microchip Technology Inc. ...
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... T (not recommended) AD bit 7-0 ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 128 • ······ 00000001 = T CY 00000000 = © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U = Unimplemented bit, read as ‘ ...
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... CH0SB3 CH0SB2 U-0 R/W-0 R/W-0 (1) (1) — CH0SA3 CH0SA2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - Preliminary © 2007 Microchip Technology Inc. R/W-0 R/W-0 (1) (1) CH0SB1 CH0SB0 bit 8 R/W-0 R/W-0 (1) (1) CH0SA1 CH0SA0 bit Bit is unknown (1) (1) ...
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... CSSL12:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Note 1: Devices with 28 pins can use only CSSL0-CSSL5 and CSSL9-CSSL12. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 ...
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... Threshold Voltage Leakage Current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch Resistance Sample/Hold Capacitance (from DAC) HOLD PIN Preliminary ≤ 5 kΩ (Typical HOLD = DAC capacitance = 4.4 pF (Typical negligible if Rs ≤ 5 kΩ. © 2007 Microchip Technology Inc. ...
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... Voltage Level © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881B-page 193 ...
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... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 194 Preliminary © 2007 Microchip Technology Inc. ...
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... V IN C2IN- C2POS C2IN REF Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY C1EN C1INV - C1 + C2EN C2INV - C2 + Preliminary CMCON< ...
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... DS39881B-page 196 R/C-0 R/W-0 C1EVT C2EN R/W-0 R/W-0 C1INV C2NEG U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ( Preliminary R/W-0 R/W-0 R/W-0 (1) (2) C1EN C2OUTEN C1OUTEN bit 8 R/W-0 R/W-0 R/W-0 C2POS C1NEG C1POS bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See Section 9.4 “Peripheral Pin Select” for more information C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2007 Microchip Technology Inc. PIC24FJ64GA004 FAMILY + IN - ...
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... PIC24FJ64GA004 FAMILY NOTES: DS39881B-page 198 Preliminary © 2007 Microchip Technology Inc. ...