PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 58

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F872
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This, then, would give
waveforms for SPI communication as shown in
Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is
transmitted first. In Master mode, the SPI clock rate (bit
rate) is user programmable to be one of the following:
• F
• F
• F
• Timer2 Output/2
FIGURE 9-2:
9.1.2
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1<3>)
is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times, as
specified in the electrical specifications.
DS30221C-page 56
SCK (CKP = 0,
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO
SDI (SMP = 0)
SDI (SMP = 1)
SSPIF
OSC
OSC
OSC
CKE = 0)
CKE = 1)
CKE = 0)
CKE = 1)
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
SLAVE MODE
CY
)
CY
CY
)
SPI MODE TIMING, MASTER MODE
)
bit7
bit7
bit7
bit6
bit5
bit4
This allows a maximum bit clock frequency (at 20 MHz)
of 5.0 MHz.
Figure 9-6 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
Note 1: When the SPI module is in Slave mode
2: If the SPI is used in Slave mode with
bit3
with
(SSPCON<3:0> = 0100), the SPI module
will reset if the SS pin is set to V
CKE = '1', then SS pin control must be
enabled.
bit2
SS
© 2006 Microchip Technology Inc.
pin
bit1
control
bit0
bit0
DD
enabled
bit0
.