PIC16F1827-I/MV Microchip Technology Inc., PIC16F1827-I/MV Datasheet - Page 246

• Manufacturer Part Number: PIC16F1827-I/MV
• Description: 28 UQFN 4x4x0.5mm TUBE, 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enha
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-I/MV

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin UQFN
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16(L)F1826/27
25.4.9
The 9th SCLx pulse for any transferred byte in I
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDAx line low. The transmitter must release con-
trol of the line during this time to shift in the response.
The Acknowledge (ACK) is an active-low signal, pull-
ing the SDAx line low indicated to the transmitter that
the device has received the transmitted data and is
ready to receive more.
The result of an ACK is placed in the ACKSTAT bit of
the SSPxCON2 register.
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPxCON2 reg-
ister is set/cleared to determine the response.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPxCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPxSTAT regis-
ter or the SSPxOV bit of the SSPxCON1 register are
set when a byte is received.
When the module is addressed, after the 8th falling
edge of SCLx on the bus, the ACKTIM bit of the
SSPxCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
DS41391D-page 246
ACKNOWLEDGE SEQUENCE
2
C is
25.5
The MSSPx Slave mode operates in one of four
modes selected in the SSPxM bits of SSPxCON1 reg-
ister. The modes can be divided into 7-bit and 10-bit
Addressing mode. 10-bit Addressing modes operate
the same as 7-bit with some additional overhead for
handling the larger addresses.
Modes with Start and Stop bit interrupts operated the
same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
condition.
25.5.1
The SSPxADD register
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPxBUF register and an
interrupt is generated. If the value does not match, the
module goes Idle and no indication is given to the soft-
ware that anything happened.
The SSPx Mask register
address matching process.
“SSPx Mask Register”
25.5.1.1
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
25.5.1.2
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the UA bit is set
and SCLx is held low until the user updates SSPxADD
with the low address. The low address byte is clocked
in and all 8 bits are compared to the low address value
in SSPxADD. Even if there is not an address match;
SSPxIF and UA are set, and SCLx is held low until
SSPxADD is updated to receive a high byte again.
When SSPxADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hard-
ware will then acknowledge the read request and pre-
pare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
I
SLAVE MODE ADDRESSES
2
C
I
I
2
2
C Slave 7-bit Addressing Mode
C Slave 10-bit Addressing Mode
SLAVE MODE OPERATION
 2011 Microchip Technology Inc.
for more information.
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See
25-6) contains the
25-5) affects the
Section 25.5.9