TJA1041T/V,512 NXP Semiconductors, TJA1041T/V,512 Datasheet - Page 8

• Manufacturer Part Number: TJA1041T/V,512
• Description: IC TXRX CAN HS 5.25V 14-SOIC
• Manufacturer: NXP Semiconductors
• Type: Transceiverr

Specifications of TJA1041T/V,512

• Number Of Drivers/receivers: 1/1
• Protocol: CAN
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935286694512; TJA1041T/V; TJA1041T/V

NXP Semiconductors
TJA1041_6
Product data sheet
7.2.1 UV
7.2.2 UV
7.2.3 Pwon flag
7.2.4 Wake-up flag
Table 5.
[1]
[2]
UV
on pin V
drops below V
will enter Sleep mode to save power and not disturb the bus. In Sleep mode the voltage
regulators connected to pin INH are disabled, avoiding the extra power consumption in
case of a short-circuit condition. After a waiting time (fixed by the same timers used for
setting UV
timers, allowing the voltage regulators to be reactivated at least until UV
UV
drops below V
save power and not disturb the bus. UV
recovered. The transceiver will then return to the operating mode determined by the logic
state of pins STB and EN.
Pwon is the V
recovered after it dropped below V
disconnected from the battery. By setting the pwon flag, the UV
cleared and the transceiver cannot enter Sleep mode. This ensures that any voltage
regulator connected to pin INH is activated when the node is reconnected to the battery. In
pwon/listen-only mode the pwon flag can be made available on pin ERR. The flag is
cleared when the transceiver enters normal mode.
The wake-up flag is set when the transceiver detects a local or a remote wake-up request.
A local wake-up request is detected when a logic state change on pin WAKE remains
stable for at least t
dominant state for at least t
go-to-sleep command mode or Sleep mode. Setting of the flag is blocked during the
UV
Internal flag
wake-up
source
bus failure
local failure
NOM
BAT
NOM
NOM
BAT
Pin ERR is an active-LOW output, so a LOW level indicates a set flag and a HIGH level indicates a cleared
flag. Allow pin ERR to stabilize for at least 8 s after changing operating modes.
Allow for a TXD dominant time of at least 4 s per dominant-recessive cycle.
is the V
is the V
flag
flag waiting time. By setting the wake-up flag, the UV
CC
flag
NOM
Accessing internal flags via pin ERR
drops below V
BAT
I/O(sleep)
BAT
BAT(stb)
) any wake-up request or setting of the pwon flag will clear UV
Flag is available on pin ERR
in normal mode (before the fourth dominant to
recessive edge on pin TXD
in normal mode (after the fourth dominant to
recessive edge on pin TXD
in pwon/listen-only mode (coming from
normal mode)
CC
power-on flag. This flag is set when the voltage on pin V
undervoltage detection flag. The flag is set when the voltage on pin V
and V
wake
. When UV
Rev. 06 — 5 December 2007
for longer than t
. A remote wake-up request is detected when the bus remains in
I/O
CC(sleep)
undervoltage detection flag. The flag is set when the voltage
BUS
. The wake-up flag can only be set in Standby mode,
BAT
for longer than t
BAT(pwon)
is set, the transceiver will try to enter Standby mode to
UV(VI/O)
[2]
[2]
BAT
)
[1]
, particularly after the transceiver was
is cleared when the voltage on pin V
. When the UV
…continued
UV(VCC)
Flag is cleared
on leaving normal mode, or by
setting the pwon flag
on re-entering normal mode
on entering normal mode or when
RXD is dominant while TXD is
recessive (provided that all local
failures are resolved)
or when the voltage on pin V
High speed CAN transceiver
NOM
NOM
NOM
flag is set, the transceiver
flag and timers are
flag and timers are
© NXP B.V. 2007. All rights reserved.
TJA1041
NOM
BAT
NOM
is set again.
has
BAT
and the
has
8 of 26
BAT
I/O