PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet
PIC18F1220-I/SO
Specifications of PIC18F1220-I/SO
Related parts for PIC18F1220-I/SO
PIC18F1220-I/SO Summary of contents
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... Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology 2004 Microchip Technology Inc. PIC18F1220/1320 18/20/28-Pin High-Performance, Data Sheet DS39605C ...
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... October 2003. The Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. L ® code hopping OQ ...
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... Instructions PIC18F1220 4K 2048 PIC18F1320 8K 4096 2004 Microchip Technology Inc. PIC18F1220/1320 Peripheral Highlights: • High current sink/source 25 mA/25 mA • Three external interrupts • Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart - Capture is 16-bit, max resolution 6 ...
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... PIC18F1220/1320 Pin Diagrams 18-Pin PDIP, SOIC RA0/AN0 1 18 RA1/AN1/LVDIN 2 17 RA4/T0CKI 3 16 MCLR/V /RA5 / RA2/AN2/V - REF 6 13 RA3/AN3 REF 8 11 RB0/AN4/INT0 RB1/AN5/TX CK/INT1 28-Pin QFN MCLR/V /RA5 RA2/AN2/V - REF DS39605C-page 2 20-Pin SSOP RA0/AN0 RB3/CCP1/P1A RA1/AN1/LVDIN RB2/P1B/INT2 RA4/T0CKI OSC1/CLKI/RA7 MCLR/V /RA5 PP OSC2/CLKO/RA6 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 295 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 295 Index .................................................................................................................................................................................................. 297 On-Line Support................................................................................................................................................................................. 305 Systems Information and Upgrade Hot Line ...................................................................................................................................... 305 Reader Response .............................................................................................................................................................................. 306 PIC18F1220/1320 Product Identification System .............................................................................................................................. 307 2004 Microchip Technology Inc. PIC18F1220/1320 DS39605C-page 3 ...
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... PIC18F1220/1320 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
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... Timer have been reduced 80%, with typical values of 1.1 and 2.1 A, respectively. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F1220/1320 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators. • ...
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... Figure 1-1. The devices are differentiated from each other only in the amount of on-chip Flash program memory (4 Kbytes for the PIC18F1220 device, 8 Kbytes for the PIC18F1320 device). These and other features are summarized in Table 1-1. TABLE 1-1: ...
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... FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM Table Pointer <2> 21 inc/dec logic 21 21 PCLATU 20 Address Latch Program Memory (4 Kbytes) PIC18F1220 (8 Kbytes) PIC18F1320 Data Latch 16 Table Latch 8 ROM Latch Instruction Register Instruction Decode & Control (2) OSC1 Power-up Timing (2) OSC2 Generation Oscillator Start-up Timer INTRC ...
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... PIC18F1220/1320 TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP/ SSOP SOIC MCLR/V /RA5 MCLR V PP RA5 OSC1/CLKI/RA7 16 18 OSC1 CLKI RA7 OSC2/CLKO/RA6 15 17 OSC2 CLKO RA6 RA0/AN0 1 1 RA0 AN0 RA1/AN1/LVDIN 2 2 RA1 AN1 LVDIN RA2/AN2 REF RA2 ...
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... TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP/ SSOP SOIC RB0/AN4/INT0 8 9 RB0 AN4 INT0 RB1/AN5/TX/CK/INT1 9 10 RB1 AN5 TX CK INT1 RB2/P1B/INT2 17 19 RB2 P1B INT2 RB3/CCP1/P1A 18 20 RB3 CCP1 P1A RB4/AN6/RX/DT/KBI0 10 11 RB4 AN6 RX DT KBI0 ...
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... PIC18F1220/1320 NOTES: DS39605C-page 10 2004 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F1220 and PIC18F1320 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL ...
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... PIC18F1220/1320 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) 2004 Microchip Technology Inc. PIC18F1220/1320 2.5 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R ...
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... PIC18F1220/1320 2.6 Internal Oscillator Block The PIC18F1220/1320 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC MHz clock source, which can be used to directly drive the system clock ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F1220/1320 devices are shown in Figure 2-8. See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 19.1 “ ...
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... The OSTS indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the system clock in Primary Clock modes. The IOFS bit indicates FIGURE 2-8: PIC18F1220/1320 CLOCK DIAGRAM Primary Oscillator OSC2 Sleep OSC1 ...
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... SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block (RC modes Timer1 oscillator (Secondary modes Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on state of the IESO bit in Configuration Register 1H. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 (1) R/W-0 R/W-0 R R-0 IRCF1 IRCF0 OSTS ...
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... PIC18F1220/1320 2.7.2 OSCILLATOR TRANSITIONS The PIC18F1220/1320 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources ...
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... POWER MANAGED MODES The PIC18F1220/1320 devices offer a total of six oper- ating modes for more efficient power management (see Table 3-1). These provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery powered devices). There are three categories of power managed modes: • ...
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... PIC18F1220/1320 3.1.2 ENTERING POWER MANAGED MODES In general, entry, exit and switching between power managed clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power managed clock sources ...
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... INTOSC multiplexer 3.2 Sleep Mode The power managed Sleep mode in the PIC18F1220/ 1320 devices is identical to that offered in all other PICmicro microcontrollers entered by clearing the IDLEN and SCS1:SCS0 bits (this is the Reset state) and executing the SLEEP instruction. This shuts down the primary oscillator and the OSTS bit is cleared (see Figure 3-1) ...
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... PIC18F1220/1320 FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE OSC1 CPU Clock Peripheral Clock Sleep Program PC Counter FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake Event Note 1024 T ...
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... Program PC Counter Wake Event 2004 Microchip Technology Inc. PIC18F1220/1320 When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately required between the wake event and code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake- up, the OSTS bit remains set ...
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... PIC18F1220/1320 3.3.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the Idle bit, modifying bits, SCS1:SCS0 = 01 and executing a SLEEP instruction. When the clock source is switched (see Figure 3-5) to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set ...
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... OST OSC PLL 2004 Microchip Technology Inc. PIC18F1220/1320 instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source ...
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... PIC18F1220/1320 3.4 Run Modes If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source ...
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... CPU Clock Peripheral Clock Program PC Counter 2004 Microchip Technology Inc. PIC18F1220/1320 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... PIC18F1220/1320 3.4.4 EXIT TO IDLE MODE An exit from a power managed Run mode to its corresponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). ...
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... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). 2004 Microchip Technology Inc. PIC18F1220/1320 Power Activity during Wake-up from Clock Ready Managed ...
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... PIC18F1220/1320 3.5.2 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 19.3 “ ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. 2004 Microchip Technology Inc. PIC18F1220/1320 3.6.3 EXAMPLE – CCP IN CAPTURE MODE A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i ...
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... PIC18F1220/1320 NOTES: DS39605C-page 32 2004 Microchip Technology Inc. ...
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... RESET The PIC18F1220/1320 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “ ...
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... Overstress (EOS). 4.2 Power-up Timer (PWRT) The Power-up Timer (PWRT) of the PIC18F1220/1320 is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay will vary from chip-to-chip due temperature and process variation ...
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... Legend unchanged unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2004 Microchip Technology Inc. PIC18F1220/1320 (2) Power-up and Brown-out PWRTEN = 1 ...
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... PIC18F1220/1320 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Register Devices TOSU 1220 1320 TOSH 1220 1320 TOSL 1220 1320 STKPTR 1220 1320 PCLATU 1220 1320 PCLATH 1220 1320 PCL 1220 1320 TBLPTRU 1220 1320 TBLPTRH 1220 1320 TBLPTRL 1220 1320 ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 5 of PORTA is enabled if MCLR is disabled. 2004 Microchip Technology Inc. PIC18F1220/1320 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F1220/1320 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Register Devices TMR3H 1220 1320 TMR3L 1220 1320 T3CON 1220 1320 SPBRGH 1220 1320 SPBRG 1220 1320 RCREG 1220 1320 TXREG 1220 1320 TXSTA 1220 1320 RCSTA 1220 1320 BAUDCTL 1220 ...
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... V DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2004 Microchip Technology Inc. PIC18F1220/1320 DD T PWRT T OST T PWRT T OST T PWRT T OST , V RISE < ...
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... PIC18F1220/1320 FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. ...
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... NOP instruction). The PIC18F1220 has 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F1320 has 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. ...
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... PIC18F1220/1320 5.2 Return Address Stack The return address stack allows any combination program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 R/W-0 R/W-0 — ...
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... PIC18F1220/1320 5.3 Fast Register Stack A “fast return” option is available for interrupts. A fast register stack is provided for the Status, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt ...
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... All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. PIC18F1220/1320 5.6 Instruction Flow/Pipelining An “ ...
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... Instruction 2: GOTO Instruction 3: MOVFF 5.7.1 TWO-WORD INSTRUCTIONS PIC18F1220/1320 devices have instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. ...
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... Figure 5-6 shows the data memory organization for the PIC18F1220/1320 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR< ...
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... PIC18F1220/1320 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F1220/1320 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh = 0001 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh DS39605C-page 48 Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh Unused Read ‘00h’ EFFh F00h Unused F7Fh ...
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... CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 5-1 and Table 5-2. TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F1220/1320 DEVICES Address Name Address FFFh ...
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... PIC18F1220/1320 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF — PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte T1CON RD16 T1RUN T1CKPS1 TMR2 Timer2 Register PR2 Timer2 Period Register T2CON — TOUTPS3 TOUTPS2 ADRESH A/D Result Register High Byte ...
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... PIC18F1220/1320 5.10 Access Bank The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: • Intermediate computational values • Local variables of subroutines • ...
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... FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2004 Microchip Technology Inc. PIC18F1220/1320 If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all ‘0’s are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected ...
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... PIC18F1220/1320 FIGURE 5-8: INDIRECT ADDRESSING OPERATION Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 5-9: INDIRECT ADDRESSING Indirect Addressing 3 11 Location Select Note 1: For register file map detail, see Table 5-1. DS39605C-page 54 0h RAM Address FFFh 12 File Address = Access of an Indirect Addressing Register ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status reg- ister, because these instructions do not affect the bits in the Status register. ...
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... PIC18F1220/1320 5.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 5-3: RCON REGISTER R/W-0 IPEN ...
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... Note 1: Table Pointer points to a byte in program memory. 2004 Microchip Technology Inc. PIC18F1220/1320 The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
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... PIC18F1220/1320 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Read completed Legend Readable bit W = Writable bit x = Bit is unknown 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR ...
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... PIC18F1220/1320 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The table latch is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory ...
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... MOVFW TABLAT MOVWF WORD_ODD 2004 Microchip Technology Inc. PIC18F1220/1320 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
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... PIC18F1220/1320 6.4 Erasing Flash Program Memory The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. ...
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... CFGS bit to access program memory; • set WREN bit to enable byte writes. 2004 Microchip Technology Inc. PIC18F1220/1320 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction must be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written ...
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... PIC18F1220/1320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVF TABLAT, W MOVWF POSTINC0 DECFSZ COUNTER GOTO READ_BLOCK ...
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... Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2004 Microchip Technology Inc. PIC18F1220/1320 ; get low byte of buffer data and increment FSR0 ; present data to table latch ; short write ; to internal TBLWT holding register, increment TBLPTR ...
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... PIC18F1220/1320 NOTES: DS39605C-page 66 2004 Microchip Technology Inc. ...
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... EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. 2004 Microchip Technology Inc. PIC18F1220/1320 Control bit, CFGS, determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations range ...
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... PIC18F1220/1320 REGISTER 7-1: EECON1 REGISTER R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘ ...
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... SLEEP BCF EECON1, WREN 2004 Microchip Technology Inc. PIC18F1220/1320 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
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... PIC18F1220/1320 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in configuration words. External read operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect configuration bit. Refer to Section 19.0 “ ...
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... HARDWARE MULTIPLIER 8.1 Introduction hardware multiplier is included in the ALU of the PIC18F1220/1320 devices. By making the multiply a hardware operation, it completes in a single instruc- tion cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the Status register ...
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... PIC18F1220/1320 Example 8-3 shows the sequence unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L 16 = (ARG1H ARG2H (ARG1H ARG2L (ARG1L ARG2H (ARG1L ARG2L) EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE ...
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... INTERRUPTS The PIC18F1220/1320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress ...
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... PIC18F1220/1320 FIGURE 9-1: INTERRUPT LOGIC INT0IF INT0IE ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation INT0IF INT0IE ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts DS39605C-page 74 TMR0IF TMR0IE TMR0IP RBIF RBIE ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
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... PIC18F1220/1320 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge ...
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... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 R/W-0 U-0 — ...
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... PIC18F1220/1320 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 U-0 R/W-0 — ...
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... TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 R/W-0 U-0 — — EEIF — ...
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... PIC18F1220/1320 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. ...
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... Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 R/W-0 U-0 — — EEIE — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 84
... PIC18F1220/1320 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 85
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 R/W-1 U-0 — — EEIP — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 86
... PIC18F1220/1320 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from a low-power mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-10: RCON REGISTER R/W-0 IPEN bit 7 bit 7 IPEN: Interrupt Priority Enable bit ...
Page 87
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2004 Microchip Technology Inc. PIC18F1220/1320 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit, TMR0IF. In 16-bit mode, an overflow (FFFFh in the TMR0H:TMR0L registers will set flag bit, TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 88
... PIC18F1220/1320 NOTES: DS39605C-page 86 2004 Microchip Technology Inc. ...
Page 89
... Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. 2004 Microchip Technology Inc. PIC18F1220/1320 The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA ...
Page 90
... PIC18F1220/1320 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 PINS RD LATA Data Bus LATA or PORTA CK Q Data Latch TRISA Q CK Analog Input TRIS Latch Mode RD TRISA PORTA To A/D Converter and LVD Modules Note 1: I/O pins have protection diodes to V FIGURE 10-3: BLOCK DIAGRAM OF OSC2/CLKO/RA6 PIN ...
Page 91
... Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: RA5 is an input only if MCLR is disabled. 2004 Microchip Technology Inc. PIC18F1220/1320 Schmitt Trigger Latch ...
Page 92
... PIC18F1220/1320 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 93
... Analog Input Mode Data Bus WR LATB or PORTB WR TRISB RD PORTB Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2004 Microchip Technology Inc. PIC18F1220/1320 1 0 Data Latch TRIS Latch TRISB ...
Page 94
... PIC18F1220/1320 FIGURE 10-9: BLOCK DIAGRAM OF RB2/P1B/INT2 PIN P1B Enable P1B Data P1B/D Tri-State Auto-Shutdown Data Bus WR LATB or PORTB WR TRISB RD PORTB INT2 Input Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). ...
Page 95
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: ECCP1 pin output enable active for any PWM mode and Compare mode, where CCP1M<3:0> = 1000 or 1001. 4: ECCP1 pin input enable active for Capture mode only. 2004 Microchip Technology Inc. PIC18F1220/1320 ...
Page 96
... PIC18F1220/1320 FIGURE 10-11: BLOCK DIAGRAM OF RB4/AN6/RX/DT/KBI0 PIN EUSART Enabled Analog Input Mode DT TRIS DT Data RD LATB Data Bus D WR LATB or PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISB RD PORTB Set RBIF From other RB7:RB4 pins To A/D Converter Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2< ...
Page 97
... From other RB7:RB5 and RB4 pins RB7:RB5 in Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2004 Microchip Technology Inc. PIC18F1220/1320 V DD Weak P Pull-up Data Latch ...
Page 98
... PIC18F1220/1320 FIGURE 10-13: BLOCK DIAGRAM OF RB6/PGC/T1OSO/T13CKI/P1C/KBI2 PIN ECCP1 P1C/D Enable (2) RBPU P1B/D Tri-State Auto-Shutdown P1C Data RD LATB Data Bus LATB or PORTB CK Q Data Latch TRISB CK Q TRIS Latch RD TRISB T1OSCEN RD PORTB Set RBIF From other RB7:RB4 pins PGC T13CKI Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2< ...
Page 99
... TRIS Latch RD TRISB T1OSCEN RD PORTB Set RBIF From other RB7:RB4 pins PGD Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2004 Microchip Technology Inc. PIC18F1220/1320 V DD Weak P Pull- TTL ...
Page 100
... PIC18F1220/1320 TABLE 10-3: PORTB FUNCTIONS Name Bit# RB0/AN4/INT0 bit 0 RB1/AN5/TX/CK/INT1 bit 1 RB2/P1B/INT2 bit 2 RB3/CCP1/P1A bit 3 RB4/AN6/RX/DT/KBI0 bit 4 RB5/PGM/KBI1 bit 5 RB6/PGC/T1OSO/T13CKI/ bit 6 P1C/KBI2 RB7/PGD/T1OSI/P1D/KBI3 bit 7 Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a TTL input when configured as a port input pin. ...
Page 101
... Prescale value Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 102
... PIC18F1220/1320 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE OSC RA4/T0CKI pin 1 T0SE T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE RA4/T0CKI F /4 OSC 0 pin 1 Programmable Prescaler T0SE ...
Page 103
... Legend unknown unchanged, – = unimplemented locations read as Note 1: RA6 and RA7 are enabled as I/O pins, depending on the oscillator mode selected in Configuration Word 1H. 2004 Microchip Technology Inc. PIC18F1220/1320 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution) ...
Page 104
... PIC18F1220/1320 NOTES: DS39605C-page 102 2004 Microchip Technology Inc. ...
Page 105
... Stops Timer1 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 106
... PIC18F1220/1320 12.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). FIGURE 12-1: TIMER1 BLOCK DIAGRAM TMR1IF Overflow Interrupt Flag bit TMR1H T1OSC T13CKI/T1OSO T1OSI Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off ...
Page 107
... If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead), or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation. 2004 Microchip Technology Inc. PIC18F1220/1320 FIGURE 12-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR C1 PGD ...
Page 108
... PIC18F1220/1320 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
Page 109
... MOVWF hours RETURN 2004 Microchip Technology Inc. PIC18F1220/1320 Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals necessary to pre- load it; the simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered ...
Page 110
... PIC18F1220/1320 TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 — ADIF RCIF PIE1 — ADIE RCIE IPR1 — ADIP RCIP TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register ...
Page 111
... Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 112
... PIC18F1220/1320 13.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: ...
Page 113
... Stops Timer3 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 114
... PIC18F1220/1320 14.1 Timer3 Operation Timer3 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). FIGURE 14-1: TIMER3 BLOCK DIAGRAM TMR3IF Overflow Interrupt Flag bit TMR3H T1OSC T1OSO/ ...
Page 115
... T3CON RD16 — T3CKPS1 T3CKPS0 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2004 Microchip Technology Inc. PIC18F1220/1320 14.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. See Section 15.4.4 “ ...
Page 116
... PIC18F1220/1320 NOTES: DS39605C-page 114 2004 Microchip Technology Inc. ...
Page 117
... PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 The control register for CCP1 is shown in Register 15-1. In addition to the expanded functions of the CCP1CON register, the ECCP module has two additional registers associated with Enhanced PWM operation ...
Page 118
... PIC18F1220/1320 15.1 ECCP Outputs The Enhanced CCP module may have up to four outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTB. The pin assignments are summarized in Table 15-1. TABLE 15-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES ...
Page 119
... RB3/CCP1/P1A compare output latch to the default low level. This is not the PORTB I/O data latch. 2004 Microchip Technology Inc. PIC18F1220/1320 recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. ...
Page 120
... PIC18F1220/1320 FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3, but does not set Timer1 or Timer3 interrupt flag bit and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion. Special Event Trigger Q S RB3/CCP1/P1A pin R TRISB<3> Output Enable ...
Page 121
... Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2004 Microchip Technology Inc. PIC18F1220/1320 15.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON< ...
Page 122
... PIC18F1220/1320 FIGURE 15-3: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H (Slave) R Comparator (Note 1) TMR2 S Comparator Clear Timer, set CCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler to create the 10-bit time base ...
Page 123
... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 15.5.6 “Programmable Dead-Band Delay”). 2004 Microchip Technology Inc. PIC18F1220/1320 0 Duty Cycle Period (1) (1) Delay Delay PR2+1 DS39605C-page 121 ...
Page 124
... FIGURE 15-7: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) PIC18F1220/1320 Half-Bridge Output Driving a Full-Bridge Circuit PIC18F1220/1320 P1A P1B DS39605C-page 122 The TRISB<3> and TRISB<2> bits must be cleared to configure P1A and P1B as outputs. ...
Page 125
... P1B P1C P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2004 Microchip Technology Inc. PIC18F1220/1320 The TRISB<3:2> and TRISB<7:6> bits must be cleared to make the P1A, P1B, P1C and P1D pins output. Period Duty Cycle Period Duty Cycle ...
Page 126
... PIC18F1220/1320 FIGURE 15-9: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F1220/1320 P1A P1B P1C P1D 15.5.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the Forward/Reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
Page 127
... External Switch D Potential Shoot-Through Current Note the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF 2004 Microchip Technology Inc. PIC18F1220/1320 (1) PWM Period DC One Timer2 Count Forward Period t1 DC PWM Period (2) Reverse Period ...
Page 128
... PIC18F1220/1320 15.5.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on ...
Page 129
... PSSBDn: Pins B and D Shutdown State Control bits 00 = Drive Pins B and D to ‘0’ Drive Pins B and D to ‘1’ Pins B and D tri-state Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 PSSAC0 W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 130
... PIC18F1220/1320 15.5.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module, following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 15-12), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 131
... Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRISB bits. • Clear the ECCPASE bit (ECCPAS<7>). 2004 Microchip Technology Inc. PIC18F1220/1320 15.5.10 OPERATION IN LOW-POWER MODES In the Low-Power Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change ...
Page 132
... PIC18F1220/1320 TABLE 15-5: REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2 Name Bit 7 Bit 6 Bit 5 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN — — PIR1 — ADIF RCIF PIE1 — ADIE RCIE IPR1 — ADIP RCIP TMR2 Timer2 Module Register PR2 Timer2 Module Period Register T2CON — ...
Page 133
... These are detailed in on the following pages in Register 16-1, Register 16-2 and respectively. 2004 Microchip Technology Inc. PIC18F1220/1320 16.1 Asynchronous Operation in Power Managed Modes The EUSART may operate in Asynchronous mode while the peripheral clocks are being provided by the internal oscillator block. This makes it possible to ...
Page 134
... PIC18F1220/1320 REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 CSRC bit 7 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode Master mode (clock generated internally from BRG Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit ...
Page 135
... Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 136
... PIC18F1220/1320 REGISTER 16-3: BAUDCTL: BAUD RATE CONTROL REGISTER U-0 — RCIDL bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receiver is Idle 0 = Receiver is busy bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode ...
Page 137
... Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% 2004 Microchip Technology Inc. PIC18F1220/1320 16.2.1 POWER MANAGED MODE OPERATION The system clock is used to generate the desired baud rate; however, when a power managed mode is entered, the clock source may be operating at a differ- ent frequency than in PRI_RUN mode ...
Page 138
... PIC18F1220/1320 TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 TXSTA CSRC TX9 TXEN RCSTA SPEN RX9 SREN BAUDCTL — RCIDL — SPBRGH Baud Rate Generator Register High Byte SPBRG Baud Rate Generator Register Low Byte Legend unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. ...
Page 139
... Microchip Technology Inc. PIC18F1220/1320 SYNC = 0, BRGH = 1, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (K) (decimal) — — ...
Page 140
... PIC18F1220/1320 TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD F = 40.000 MHz OSC RATE Actual SPBRG Actual (K) % Rate value Error (K) (decimal) 0.3 0.300 0.00 33332 1.2 1.200 0.00 8332 2.4 2.400 0.02 4165 9.6 9.606 ...
Page 141
... RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. 2004 Microchip Technology Inc. PIC18F1220/1320 Note the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. ...
Page 142
... PIC18F1220/1320 FIGURE 16-1: AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h BRG Value RX pin BRG Clock Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG SPBRGH Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. 16.3 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA< ...
Page 143
... Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) 2004 Microchip Technology Inc. PIC18F1220/1320 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. ...
Page 144
... PIC18F1220/1320 FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) RB1/AN5/TX/ Start bit CK/INT1 (pin TXIF bit (Interrupt Reg. Flag) TRMT bit Word 1 (Transmit Shift Transmit Shift Reg. Reg. Empty Flag) Note: This timing diagram shows two consecutive transmissions. ...
Page 145
... SPBRGH SPBRG Baud Rate Generator RB4/AN6/RX/DT/KBI0 Pin Buffer and Control SPEN 2004 Microchip Technology Inc. PIC18F1220/1320 16.3.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate ...
Page 146
... PIC18F1220/1320 To set up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate high-speed baud rate is desired, set bit BRGH (see Section 16.2 “EUSART Baud Rate Generator (BRG)”). 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. ...
Page 147
... If the wake-up event requires a long oscillator warm-up time, the WUE bit may be cleared while the primary clock is still starting. 2: The EUSART remains in Idle while the WUE bit is set. 2004 Microchip Technology Inc. PIC18F1220/1320 and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 devices, or 000h (12 bits) for LIN bus ...
Page 148
... PIC18F1220/1320 16.3.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break char- acter transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA< ...
Page 149
... BRG Output (Shift Clock) TX (pin) Start Bit TXIF bit TRMT bit SENDB 2004 Microchip Technology Inc. PIC18F1220/1320 7. Enable Auto-Baud Rate Detect. Set ABDEN. 8. Return from the interrupt. Allow the primary clock to start and stabilize (PRI_RUN or PRI_IDLE). 9. When the next RCIF interrupt occurs, the received baud rate has been measured ...
Page 150
... PIC18F1220/1320 16.4 EUSART Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA< ...
Page 151
... SPBRGH Baud Rate Generator Register High Byte SPBRG Baud Rate Generator Register Low Byte Legend unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. 2004 Microchip Technology Inc. PIC18F1220/1320 bit 0 bit 2 bit 1 Bit 4 Bit 3 ...
Page 152
... PIC18F1220/1320 16.4.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RB4/AN6/RX/DT/KBI0 pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received ...
Page 153
... Baud Rate Generator Register High Byte SPBRG Baud Rate Generator Register Low Byte Legend unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. 2004 Microchip Technology Inc. PIC18F1220/1320 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE ...
Page 154
... PIC18F1220/1320 16.5 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RB1/AN5/TX/CK/INT1 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode ...
Page 155
... Legend unknown, = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. 2004 Microchip Technology Inc. PIC18F1220/1320 To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC ...
Page 156
... PIC18F1220/1320 NOTES: DS39605C-page 154 2004 Microchip Technology Inc. ...
Page 157
... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) converter module has seven inputs for the PIC18F1220/1320 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and to set the GO/DONE bit immediately ...
Page 158
... PIC18F1220/1320 REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 — PCFG6 bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 PCFG6: A/D Port Configuration bit – AN6 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ ...
Page 159
... A/D RC oscillator) RC Note: If the A/D F added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 R/W-0 R/W-0 — ACQT2 ACQT1 ACQT0 (1) ...
Page 160
... PIC18F1220/1320 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AV and the voltage level on the DD SS RA3/AN3/V + and RA2/AN2/V - pins. REF REF The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To oper- ate in Sleep, the A/D conversion clock must be derived from the A/D’ ...
Page 161
... C = sample/hold capacitance (from DAC) HOLD R = sampling switch resistance SS 2004 Microchip Technology Inc. PIC18F1220/1320 A/D Conversion: 1. Configure the A/D module: • Configure analog pins, voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D acquisition time (ADCON2) • ...
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... PIC18F1220/1320 17.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 17-2. The source impedance (R ) and the internal sampling ...
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... T (approximately 2 s, see parameter 130 AD for more information). Table 17-1 shows the resultant T the device operating frequencies and the A/D clock source selected. ) Maximum Device Frequency PIC18F1220/1320 1.25 MHz 000 2.50 MHz 100 5.00 MHz 001 10.0 MHz 101 20.0 MHz 010 40 ...
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... PIC18F1220/1320 17.5 Operation in Low-Power Modes The selection of the automatic acquisition time and the A/D conversion clock is determined, in part, by the low- power mode clock source and frequency while in a low-power mode. If the A/D is expected to operate while the device low-power mode, the ACQT2:ACQT0 and ...
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... Set GO bit (Holding capacitor continues acquiring input) 2004 Microchip Technology Inc. PIC18F1220/1320 Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion ...
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... PIC18F1220/1320 17.8 Use of the CCP1 Trigger An A/D conversion can be started by the “special event trigger” of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro- grammed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the ...
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... Time 2004 Microchip Technology Inc. PIC18F1220/1320 Figure 18-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage V the LVD logic generates an interrupt. This occurs at time T . The application software then has the time, ...
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... PIC18F1220/1320 FIGURE 18-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM V DD LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits, LVDL3:LVDL0, are set to ‘1111’. In this state, the com- ...
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... Reserved 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R-0 R/W-0 R/W-0 — IRVST LVDEN LVDL3 W = Writable bit U = Unimplemented bit, read as ‘ ...
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... PIC18F1220/1320 18.2 Operation Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current require- ments, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked ...
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... The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter D022B. 2004 Microchip Technology Inc. PIC18F1220/1320 18.3 Operation During Sleep When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wake- up from Sleep ...
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... PIC18F1220/1320 NOTES: DS39605C-page 170 2004 Microchip Technology Inc. ...
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... Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F1220/1320 devices have a Watchdog Timer, which is either permanently enabled via the configuration bits, or software controlled (if configured as disabled). ...
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... PIC18F1220/1320 REGISTER 19-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-1 R/P-1 IESO FSCM bit 7 bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled bit 6 FSCM: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled ...
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... PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend Readable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 R/P-1 — — — BORV1 (1) ...
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... PIC18F1220/1320 REGISTER 19-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 — bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 ...
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... Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead) or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation. 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 U-0 U-0 — ...
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... Block 0 (00200-000FFFh) not code-protected 0 = Block 0 (00200-000FFFh) code-protected bit 1 CP1: Code Protection bit (PIC18F1220 Block 1 (000800-000FFFh) not code-protected 0 = Block 1 (000800-000FFFh) code-protected bit 0 CP0: Code Protection bit (PIC18F1220 Block 0 (000200-0007FFh) not code-protected 0 = Block 0 (000200-0007FFh) code-protected Legend Readable bit -n = Value when device is unprogrammed REGISTER 19-7: ...
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... Block 1 (001000-001FFFh) write-protected bit 0 WRT0: Write Protection bit (PIC18F1320 Block 0 (00200-000FFFh) not write-protected 0 = Block 0 (00200-000FFFh) write-protected bit 1 WRT1: Write Protection bit (PIC18F1220 Block 1 (000800-000FFFh) not write-protected 0 = Block 1 (000800-000FFFh) write-protected bit 0 WRT0: Write Protection bit (PIC18F1220 Block 0 (000200-0007FFh) not write-protected 0 = Block 0 (000200-0007FFh) write-protected ...
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... Block 1 (000800-000FFFh) not protected from table reads executed in other blocks 0 = Block 1 (000800-000FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit (PIC18F1220 Block 0 (000200-0007FFh) not protected from table reads executed in other blocks 0 = Block 0 (000200-0007FFh) protected from table reads executed in other blocks ...
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... REGISTER 19-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1220/1320 DEVICES R DEV2 DEV1 bit 7 bit 7-5 DEV2:DEV0: Device ID bits 111 = PIC18F1220 110 = PIC18F1320 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend Read-only bit -n = Value when device is unprogrammed REGISTER 19-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F1220/1320 DEVICES ...
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... PIC18F1220/1320 19.2 Watchdog Timer (WDT) For PIC18F1220/1320 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler ...
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... Program PC Counter Wake from Interrupt Event Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2004 Microchip Technology Inc. PIC18F1220/1320 Bit 5 Bit 4 Bit 3 — WDTPS3 WDTPS2 — — — — In all other power managed modes, Two-Speed Start-up is not used ...
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... PIC18F1220/1320 19.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the micro- controller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FSCM (CONFIG1H<6>). ...
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... OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2004 Microchip Technology Inc. PIC18F1220/1320 19.4.3 FSCM INTERRUPTS IN POWER MANAGED MODES As previously mentioned, entering a power managed mode clears the Fail-Safe condition ...
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... PIC18F1220/1320 19.4.4 POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or Low-Power Sleep mode. When the primary system clock is EC INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL XT), the situation is somewhat dif- ferent ...
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... PICmicro devices. The user program memory is divided into three blocks. One of these is a boot block of 512 bytes. The remain- der of the memory is divided into two blocks on binary boundaries. FIGURE 19-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320 Block Code Protection Address Controlled By: Range ...
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... PIC18F1220/1320 19.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to, or written from, any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions. ...
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... EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED: PIC18F1320 Register Values TBLPTR = 0002FFh PC = 0007FEh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. 2004 Microchip Technology Inc. PIC18F1220/1320 Program Memory Configuration Bit Settings 000000h 0001FFh 000200h 000FFFh ...
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... The ID locations can be read when the device is code-protected. 19.7 In-Circuit Serial Programming PIC18F1220/1320 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage ...
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... SS execution. 2004 Microchip Technology Inc. PIC18F1220/1320 If Low-Voltage Programming mode will not be used, the LVP bit can be cleared and RB5/PGM/KBI1 becomes available as the digital I/O pin RB5. The LVP bit may be set or cleared only when using standard high-voltage ...
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... PIC18F1220/1320 NOTES: DS39605C-page 190 2004 Microchip Technology Inc. ...
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... The desired FSR register to load the literal value into (specified by ‘f’) • No operand required (specified by ‘—’) 2004 Microchip Technology Inc. PIC18F1220/1320 The control instructions may use some of the following operands: • A program memory address (specified by ‘n’) • The mode of the CALL or RETURN instructions (specified by ‘ ...
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... PIC18F1220/1320 TABLE 20-1: OPCODE FIELD DESCRIPTIONS Field RAM access bit RAM location in Access RAM (BSR register is ignored RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). bbb Bank Select Register. Used to select the current RAM bank. BSR Destination select bit ...
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... Control operations CALL, GOTO and Branch operations 15 OPCODE 1111 n = 20-bit immediate value 15 OPCODE Fast bit OPCODE 15 OPCODE 2004 Microchip Technology Inc. PIC18F1220/1320 Example Instruction ADDWF MYREG (FILE #) 0 f (Source FILE #) MOVFF MYREG1, MYREG2 0 f (Destination FILE #) (FILE #) BSF MYREG, bit ...
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... PIC18F1220/1320 TABLE 20-1: PIC18FXXXX INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF Add WREG and f ADDWFC Add WREG and Carry bit to f ANDWF AND WREG with f CLRF f, a Clear f COMF Complement f CPFSEQ f, a Compare f with WREG, skip = CPFSGT f, a Compare f with WREG, skip > ...
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... This ensures that all program memory locations have a valid instruction the table write starts the write cycle to internal memory, the write will continue until terminated. 2004 Microchip Technology Inc. PIC18F1220/1320 16-Bit Instruction Word Cycles MSb ...
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... PIC18F1220/1320 TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) Mnemonic, Description Operands LITERAL OPERATIONS ADDLW k Add literal and WREG ANDLW k AND literal with WREG IORLW k Inclusive OR literal with WREG LFSR f, k Move literal (12-bit) 2nd word to FSRx MOVLB k Move literal to BSR<3:0> MOVLW k Move literal to WREG ...
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... Q2 Q3 Decode Read Process literal ‘k’ Data Example: ADDLW 0x15 Before Instruction W = 0x10 After Instruction W = 0x25 2004 Microchip Technology Inc. PIC18F1220/1320 ADDWF k Syntax: Operands: Operation: kkkk kkkk Status Affected: Encoding: Description: Q4 Words: Write to W Cycles: Q Cycle Activity: Q1 Decode Example: ...
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... PIC18F1220/1320 ADDWFC ADD W and Carry bit to f Syntax: [ label ] ADDWFC Operands 255 d [0,1] a [0,1] Operation: (W) + (f) + (C) dest Status Affected: N, OV, C, DC, Z Encoding: 0010 00da Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed ‘d’ is ‘1’, the result is placed in data memory location ‘ ...