PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 141

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.2.3
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 16-1) begins whenever a Start bit is received and
the ABDEN bit is set. The calculation is self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Detect
must receive a byte with the value 55h (ASCII “U”,
which is also the LIN bus Sync character), in order to
calculate the proper bit rate. The measurement is taken
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming sig-
nal. After a Start bit, the SPBRG begins counting up
using the preselected clock source on the first rising
edge of RX. After eight bits on the RX pin, or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH:SPBRG registers.
Once the 5th edge is seen (should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes, by checking for 00h in
the SPBRGH register. Refer to Table 16-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. RCREG content should be discarded.
 2004 Microchip Technology Inc.
AUTO-BAUD RATE DETECT
16.2.4
To receive a Sync (Auto-Baud Rate Detect):
1.
2.
3.
4.
5.
TABLE 16-4:
Note: During the ABD sequence, SPBRG and
BRG16
Note 1: It is up to the user to determine that the
0
0
1
1
Configure the EUSART for asynchronous receive.
TXEN should remain clear. SPBRGH:SPBRG
may be left as is. The controller should operate in
either PRI_RUN or PRI_IDLE.
Enable RXIF interrupts. Set RCIE, PEIE, GIE.
Enable Auto-Baud Rate Detect. Set ABDEN.
When the next RCIF interrupt occurs, the
received baud rate has been measured. Read
RCREG to clear RCIF and discard. Check
SPBRGH:SPBRG for a valid value. The
EUSART is ready for normal communications.
Return from the interrupt. Allow the primary
clock to run (PRI_RUN or PRI_IDLE).
Process subsequent RCIF interrupts normally
as in asynchronous reception. Remain in
PRI_RUN or PRI_IDLE until communications
are complete.
SPBRGH are both used as a 16-bit counter,
independent of BRG16 setting.
PIC18F1220/1320
BRGH
RECEIVING A SYNC (AUTO-BAUD
RATE DETECT)
timing and communication baud rates
feature.
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
must be taken into consideration when
using the Auto-Baud Rate Detection
0
1
0
1
BRG COUNTER CLOCK
RATES
BRG Counter Clock
F
F
F
F
OSC
OSC
OSC
OSC
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