ISP1504A1ETTM ST-Ericsson Inc, ISP1504A1ETTM Datasheet - Page 14

• Manufacturer Part Number: ISP1504A1ETTM
• Description: IC USB TXRX HS 36-TFBGA
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1504A1ETTM

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1504A1ET-T; ISP1504A1ET-T

NXP Semiconductors
ISP1504A1_ISP1504C1_1
Product data sheet
7.9.13 DIR
7.9.14 STP
7.9.15 NXT
7.9.16 CLOCK
7.9.17 CS_N/PWRDN
7.9.18 GND
ULPI direction output pin. Controls the direction of the data bus. By default, the
ISP1504x1 holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the
ISP1504x1 listens for data from the link. The ISP1504x1 pulls DIR to HIGH only when it
has data to send to the link, which is for one of two reasons:
For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet
or a register write operation. When DIR is asserted, the link can optionally assert STP to
abort the ISP1504x1, causing it to de-assert DIR in the next clock cycle. A weak pull-up
resistor is incorporated into the STP pin as part of the interface protect feature. For details,
see
For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
ULPI next data output pin. The ISP1504x1 holds NXT at LOW, by default. When DIR is
LOW and the link is sending data to the ISP1504x1, NXT will be asserted to notify the link
to provide the next data byte. When DIR is HIGH and the ISP1504x1 is sending data to
the link, NXT will be asserted to notify the link that another valid byte is on the bus. NXT is
not used for register read data or the RXCMD status update.
For details on NXT usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
A 60 MHz interface clock to synchronize the ULPI bus.
Active LOW chip select pin. When CS_N/PWRDN is HIGH, ULPI output pins DATA[7:0],
CLOCK, DIR and NXT are 3-stated and ignored. All internal circuits, including the internal
regulator, are powered down. When CS_N/PWRDN is LOW, the ISP1504x1 will wake up
and the ULPI bus will operate normally.
If CS_N/PWRDN is not used, it must be connected to LOW. For more information on using
CS_N/PWRDN, see
Power and signal ground. To ensure correct operation of the ISP1504x1, GND must be
soldered to the cleanest ground available.
•
•
To send the USB receive data, RXCMD status updates and register read data to the
link.
To block the link from driving the data bus during power-up, reset and low-power
mode (suspend).
Section
9.3.1.
Section
Rev. 01 — 6 August 2007
9.3.3.
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
© NXP B.V. 2007. All rights reserved.
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