PIC16F1826-I/SS Microchip Technology Inc., PIC16F1826-I/SS Datasheet - Page 400

• Manufacturer Part Number: PIC16F1826-I/SS
• Description: 20 SSOP .209in TUBE, 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhan
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1826-I/SS

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 15
• Interface: I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SSOP
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16(L)F1826/27
SSP2CON3 Register........................................................... 30
SSP2MSK Register............................................................. 30
SSP2STAT Register ........................................................... 30
SSPxADD Register ........................................................... 283
SSPxCON1 Register......................................................... 280
SSPxCON2 Register......................................................... 281
SSPxCON3 Register......................................................... 282
SSPxMSK Register ........................................................... 283
SSPxOV ............................................................................ 268
SSPxOV Status Flag......................................................... 268
SSPxSTAT Register.......................................................... 279
Stack ................................................................................... 37
Stack Overflow/Underflow................................................... 76
STATUS Register................................................................ 21
SUBWFB........................................................................... 337
T
T1CON Register.......................................................... 28, 185
T1GCON Register............................................................. 186
T2CON Register............................................................ 28, 32
Temperature Indicator Module .......................................... 137
Thermal Considerations .................................................... 352
Timer0 ....................................................................... 173, 192
Timer1 ............................................................................... 177
Timer2
Timer2/4/6 ......................................................................... 189
Timers
Timing Diagrams
DS41391D-page 400
R/W Bit ...................................................................... 247
Accessing.................................................................... 37
Reset........................................................................... 39
Associated Registers ................................................ 176
Operation .................................................................. 173
Specifications ............................................................ 360
Associated registers.................................................. 187
Asynchronous Counter Mode ................................... 179
Clock Source Selection ............................................. 178
Interrupt..................................................................... 181
Operation .................................................................. 178
Operation During Sleep ............................................ 181
Oscillator ................................................................... 179
Prescaler ................................................................... 179
Specifications ............................................................ 360
Timer1 Gate
TMR1H Register ....................................................... 177
TMR1L Register ........................................................ 177
Associated registers.................................................. 192
Associated registers.................................................. 192
Timer1
Timer2/4/6
A/D Conversion ......................................................... 362
A/D Conversion (Sleep Mode) .................................. 362
Acknowledge Sequence ........................................... 270
Asynchronous Reception .......................................... 292
Asynchronous Transmission ..................................... 288
Asynchronous Transmission (Back to Back) ............ 288
Auto Wake-up Bit (WUE) During Normal Operation . 304
Auto Wake-up Bit (WUE) During Sleep .................... 304
Automatic Baud Rate Calibration .............................. 302
Baud Rate Generator with Clock Arbitration ............. 263
Reading and Writing ......................................... 179
Selecting Source............................................... 179
T1CON.............................................................. 185
T1GCON ........................................................... 186
TXCON ............................................................. 191
Timing Diagrams and Specifications
Timing Parameter Symbology .......................................... 353
Timing Requirements
TMR0 Register.................................................................... 28
TMR1H Register ................................................................. 28
TMR1L Register.................................................................. 28
TMR2 Register.............................................................. 28, 32
TRIS.................................................................................. 338
TRISA Register........................................................... 28, 122
BRG Reset Due to SDA Arbitration During Start
Brown-out Reset (BOR)............................................ 358
Brown-out Reset Situations ........................................ 75
Bus Collision During a Repeated Start Condition
Bus Collision During a Repeated Start Condition
Bus Collision During a Start Condition (SCL = 0) ..... 274
Bus Collision During a Stop Condition (Case 1) ....... 276
Bus Collision During a Stop Condition (Case 2) ....... 276
Bus Collision During Start Condition (SDA only) ...... 273
Bus Collision for Transmit and Acknowledge ........... 272
CLKOUT and I/O ...................................................... 356
Clock Synchronization .............................................. 260
Clock Timing ............................................................. 354
Comparator Output ................................................... 163
Enhanced Capture/Compare/PWM (ECCP)............. 360
Fail-Safe Clock Monitor (FSCM)................................. 64
First Start Bit Timing ................................................. 264
Full-Bridge PWM Output........................................... 217
Half-Bridge PWM Output .................................. 215, 222
I
I
I
I
I
INT Pin Interrupt ......................................................... 84
Internal Oscillator Switch Timing ................................ 59
PWM Auto-shutdown ................................................ 221
PWM Direction Change ............................................ 218
PWM Direction Change at Near 100% Duty Cycle... 219
PWM Output (Active-High) ....................................... 213
PWM Output (Active-Low) ........................................ 214
Repeat Start Condition ............................................. 265
Reset Start-up Sequence ........................................... 77
Reset, WDT, OST and Power-up Timer ................... 357
Send Break Character Sequence ............................. 305
SPI Master Mode (CKE = 1, SMP = 1) ..................... 365
SPI Mode (Master Mode).......................................... 237
SPI Slave Mode (CKE = 0) ....................................... 366
SPI Slave Mode (CKE = 1) ....................................... 366
Synchronous Reception (Master Mode, SREN) ....... 310
Synchronous Transmission ...................................... 307
Synchronous Transmission (Through TXEN) ........... 307
Timer0 and Timer1 External Clock ........................... 359
Timer1 Incrementing Edge ....................................... 181
Two Speed Start-up.................................................... 62
USART Synchronous Receive (Master/Slave) ......... 364
USART Synchronous Transmission (Master/Slave). 364
Wake-up from Interrupt............................................... 96
PLL Clock ................................................................. 355
I
I2C Bus Start/Stop Bits ............................................. 368
SPI Mode .................................................................. 367
2
2
2
2
2
2
C Bus Data............................................................. 368
C Bus Start/Stop Bits ............................................. 367
C Master Mode (7 or 10-Bit Transmission) ............ 267
C Master Mode (7-Bit Reception)........................... 269
C Stop Condition Receive or Transmit Mode......... 271
C Bus Data............................................................. 369
Condition .......................................................... 274
(Case 1)............................................................ 275
(Case 2)............................................................ 275
Firmware Restart .............................................. 220
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