ISP1506BBS-S ST-Ericsson Inc, ISP1506BBS-S Datasheet - Page 29

• Manufacturer Part Number: ISP1506BBS-S
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1506BBS-S

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
ISP1506A_ISP1506B_1
Product data sheet
Fig 10. Example of register write, register read, extended register write and extended register read
DATA[3:0]
CLOCK
STP
NXT
DIR
AD indicates the address byte, and D indicates the data byte.
9.6 Register read and write operations
9.7 USB reset and high-speed detection handshake (chirp)
(REGW)
TXCMD
register write
immediate
Figure 10
addressing and extended addressing register operations. Extended register addressing is
optional for links. Note that register operations will be aborted if the ISP1506 unexpectedly
asserts DIR during the operation. When a register operation is aborted, the link must retry
until successful. For more information on register operations, refer to
Pin Interface (ULPI) Specification Rev.
Figure 11
handshake (chirp). The sequence is shown for hosts and peripherals.
show all RXCMD updates, and timing is not to scale. The sequence is as follows:
1. USB reset: The host detects a peripheral attachment as low-speed if DM is HIGH and
2. High-speed detection handshake (chirp)
D
as full-speed if DP is HIGH. If a host detects a low-speed peripheral, it does not follow
the remainder of this protocol. If a host detects a full-speed peripheral, it resets the
peripheral by writing to the Function Control register and setting XCVRSELECT[1:0] =
00b (high-speed) and TERMSELECT = 0b, which drives SE0 on the bus (DP and DM
connected to ground through 45 ). The host also sets OPMODE[1:0] = 10b for
correct chirp transmit and receive. The start of SE0 is labeled T
Remark: To receive chirp signaling, the host must also consider the high-speed
differential receiver output. The Host Controller must interpret LINESTATE[1:0] as
shown in
a. Peripheral chirp: After detecting SE0 for no less than 2.5 s, if the peripheral is
capable of high-speed, it sets XCVRSELECT[1:0] = 00b (high-speed) and
OPMODE[1:0] = 10b (chirp). The peripheral immediately follows this with a
TXCMD (NOPID), transmitting a Chirp K for no less than 1 ms and ending no more
shows the register read and write sequences. The ISP1506 supports immediate
shows the sequence of events for USB reset and high-speed detection
TXCMD
(EXTW) AD D
register write
extended
Table
12.
Rev. 01 — 30 May 2007
TXCMD
(REGR)
register read
immediate
1.1”.
D
ISP1506A; ISP1506B
TXCMD
(EXTW)
register read
extended
AD
ULPI HS USB OTG transceiver
D
0
.
Ref. 3 “UTMI+ Low
Figure 11
© NXP B.V. 2007. All rights reserved.
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