ICS1893BFIT IDT, Integrated Device Technology Inc, ICS1893BFIT Datasheet - Page 76

• Manufacturer Part Number: ICS1893BFIT
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893BFIT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 1893BFIT

7.11 Register 16: Extended Control Register
ICS1893BF, Rev. F, 5/13/10
Table 7-16
to customize the operations of the device.
Note:
1. For an explanation of acronyms used in
2. During any write operation to any bit in this register, the STA must write the default value to all
Table 7-16. Extended Control Register (register 16 [0x10])
† The default is the state of this pin at reset.
16.15
16.14
16.13
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
16.4
16.3
16.2
16.1
16.0
Bit
Reserved bits.
ICS1893BF Data Sheet - Release
Command Override Write
ICS reserved
ICS reserved
ICS reserved
ICS reserved
PHY Address Bit 4
PHY Address Bit 3
PHY Address Bit 2
PHY Address Bit 1
PHY Address Bit 0
Stream Cipher Test Mode Normal operation
ICS reserved
NRZ/NRZI encoding
Transmit invalid codes
ICS reserved
Stream Cipher disable
enable
lists the bits for the Extended Control Register, which the ICS1893BF provides to allow an STA
Definition
For a detailed explanation of this bit’s operation,
For a detailed explanation of this bit’s operation,
For a detailed explanation of this bit’s operation,
For a detailed explanation of this bit’s operation,
For a detailed explanation of this bit’s operation,
Read unspecified
Read unspecified
Disabled
Read unspecified
Read unspecified
Read unspecified
Read unspecified
see
see
see
see
see
NRZ encoding
Disabled
Stream Cipher enabled Stream Cipher disabled
Section 5.5, “Status
Section 5.5, “Status
Section 5.5, “Status
Section 5.5, “Status
Section 5.5, “Status
When Bit = 0
Copyright © 2009, IDT, Inc.
All rights reserved.
Table
76
7-16, see
Interface”.
Interface”.
Interface”.
Interface”.
Interface”.
Enabled
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Test mode
Read unspecified
NRZI encoding
Enabled
Read unspecified
Chapter 1, “Abbreviations and
When Bit = 1
Chapter 7 Management Register Set
RW/0
RW/0
RW/0
RW/0
RW/0
RW/0
cess
Ac-
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
SC
SF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Acronyms”.
P4RD†
P3TD†
P0AC†
P1CL†
P2LI†
fault
De-
0
0
0
0
0
0
–
1
0
0
0
May, 2010
Hex
–
–
–
8