PIC32MX440F128LT-80V/BG Microchip Technology, PIC32MX440F128LT-80V/BG Datasheet - Page 79

• Manufacturer Part Number: PIC32MX440F128LT-80V/BG
• Description: 128 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F128LT-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

TABLE 4-39:
Legend:
Note
40A0
40C0 CHEPFABT
4000 CHECON
4010 CHEACC
4020 CHETAG
4030 CHEMSK
4040
4050
4060
4070
4080
4090
1:
CHELRU
CHEMIS
CHEW0
CHEW1
CHEW2
CHEW3
CHEHIT
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
(1)
(1)
(1)
(1)
31:16
31:16 CHEWEN
31:16 LTAGBOOT
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PREFETCH REGISTERS MAP
31/15
—
—
—
—
—
30/14
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
28/12
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
LMASK<15:5>
26/10
—
—
—
—
—
—
—
LTAG<15:4>
25/9
—
—
—
—
—
—
DCSZ<1:0>
CHEPFABT<31:0>
CHELRU<15:0>
24/8
CHEMIS<31:0>
CHEW0<31:0>
CHEW1<31:0>
CHEW2<31:0>
CHEW3<31:0>
CHEHIT<31:0>
—
—
—
—
—
Bits
23/7
—
—
—
—
—
22/6
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
21/5
PREFEN<1:0>
—
—
—
—
CHELRU<24:16>
20/4
—
—
—
—
—
LTAG<23:16>
LVALID
19/3
—
—
—
—
—
LLOCK
18/2
—
—
CHEIDX<3:0>
—
—
PFMWS<2:0>
for more information.
LTYPE
17/1
—
—
—
—
CHECOH 0000
16/0
—
—
—
—
0007
0000
00xx
xxx0
xxx2
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx