DS3150TN+ Maxim Integrated Products, DS3150TN+ Datasheet

IC LIU T3/E3/STS-1 48-TQFP

DS3150TN+

Manufacturer Part Number
DS3150TN+
Description
IC LIU T3/E3/STS-1 48-TQFP
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet

Specifications of DS3150TN+

Number Of Drivers/receivers
1/1
Protocol
DS3
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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GENERAL DESCRIPTION
The DS3150 performs all the functions necessary for
interfacing at the physical layer to DS3, E3, and
STS-1 lines. The receiver performs clock and data
recovery, B3ZS/HDB3 decoding, and loss-of-signal
monitoring. The transmitter encodes outgoing data
and drives standards-compliant waveforms onto 75Ω
coaxial cable. The jitter attenuator can be mapped
into the receive path or the transmit path.
APPLICATIONS
SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators
ATM and Frame Relay Equipment
Routers
PBXs
DSLAMs
CSUs/DSUs
ORDERING INFORMATION
FUNCTIONAL DIAGRAM
DS3150QN
DS3150Q
DS3150TN
DS3150T
LINE OUT
DS3, E3,
DS3, E3,
LINE IN
PART
STS-1
STS-1
Rx+
Rx-
Tx+
Tx-
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
DS3150
LIU
RNEG
RPOS
TNEG
TPOS
RCLK
TCLK
PIN-PACKAGE
28 PLCC
28 PLCC
48 TQFP
48 TQFP
RECEIVE
CLOCK
AND DATA
TRANSMIT
CLOCK
AND DATA
3.3V, DS3/E3/STS-1 Line Interface Unit
1 of 28
FEATURES
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Pin Configurations appear at end of data sheet.
Integrated Transmitter, Receiver, and Jitter
Attenuator for DS3, E3, and STS-1
Performs Receive Clock/Data Recovery and
Transmit Waveshaping
Jitter Attenuator Can Be Placed in the Receive
Path or the Transmit Path
AGC/Equalizer Block Handles from 0dB to
15dB of Cable Loss
Interfaces to 75W Coaxial Cable at Lengths Up to
380m (DS3), 440m (E3), or 360m (STS-1)
Interfaces Directly to a DSX Monitor Signal
(20dB Flat Loss) Using Built-In Preamp
Built-In B3ZS and HDB3 Encoder/Decoder
Bipolar and NRZ Interfaces
Local and Remote Loopbacks
On-Board 2
Sequence (PRBS) Generator and Detector
Line Build-Out (LBO) Control
Transmit Line-Driver Monitor Checks for a
Faulty Transmitter or a Shorted Output
Complete DS3 AIS Generator (ANSI T1.107)
Unframed All-Ones Generator (E3 AIS)
Clock Inversion for Glueless Interfacing
Tri-State Line Driver for Low-Power Mode and
Protection Switching Applications
Loss-of-Signal (LOS) Detector (ANSI T1.231
and ITU G.775)
Automatic Data Squelching During LOS
Requires Minimal External Components
Drop-In Replacement for TDK 78P2241/B and
78P7200L (Refer to Application Note 362)
Pin Compatible with TDK 78P7200
3.3V Operation (5V Tolerant I/O), 110mA (max)
Industrial Temperature Range: -40°C to +85°C
Small Packaging: 28-Pin PLCC and
48-Pin TQFP
15
- 1 and 2
DEMO KIT AVAILABLE
23
- 1 Pseudorandom Bit
DS3150
REV: 071305

Related parts for DS3150TN+

DS3150TN+ Summary of contents

Page 1

GENERAL DESCRIPTION The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The receiver performs clock and data recovery, B3ZS/HDB3 decoding, and loss-of-signal monitoring. The transmitter encodes outgoing data and ...

Page 2

DETAILED DESCRIPTION.................................................................................................4 1.1 R .................................................................................................................................... 7 ECEIVER 1.2 T .............................................................................................................................10 RANSMITTER 1.3 D ..............................................................................................................................15 IAGNOSTICS 1 ...................................................................................................................16 ITTER TTENUATOR 2. PIN DESCRIPTIONS ........................................................................................................17 3. ELECTRICAL CHARACTERISTICS ................................................................................21 4. PIN CONFIGURATIONS ..................................................................................................25 5. PACKAGE INFORMATION..............................................................................................26 6. REVISION HISTORY ...

Page 3

Figure 1-1. Block Diagram ...........................................................................................................4 Figure 1-2. External Connections.................................................................................................6 Figure 1-3. Receiver Jitter Tolerance...........................................................................................9 Figure 1-4. E3 Waveform Template ...........................................................................................13 Figure 1-5. DS3 AIS Structure ...................................................................................................14 Figure 1-6. PRBS Output with Normal RCLK Operation ............................................................15 Figure 1-7. PRBS Output with ...

Page 4

DETAILED DESCRIPTION The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and STS-1 lines. The device has independent receive and transmit paths and a built-in jitter attenuator (Figure 1-1). The receiver performs ...

Page 5

Table 1-A. Applicable Telecommunications Standards SPECIFICATION T1.102-1993 Digital Hierarchy—Electrical Interfaces T1.107-1995 Digital Hierarchy—Formats Specification Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance T1.231-1997 Monitoring T1.404-1994 Network-to-Customer Installation—DS3 Metallic Interface Specification G.703 Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1991 Digital Multiplex Equipment ...

Page 6

Figure 1-2. External Connections TRANSMIT V 1:2ct RECEIVE 1:2ct Table 1-B. Transformer Recommendations MANUFACTURER PART NO. Pulse Engineering PE-65968 Pulse Engineering PE-65969 TG07- Halo Electronics 0206NS TD07- Halo Electronics 0206NE Note: Table subject to change. Industrial temperature range and dual ...

Page 7

Receiver Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the receiver interfaces to the incoming coaxial cable (75W) through a 1:2 step-up transformer. Figure 1-2 shows the arrangement of the transformer and ...

Page 8

For E3 LOS Assertion: 1) The ALOS circuitry detects that the incoming signal is less than or equal to a signal level approximately 24dB below nominal and mutes the data coming out of the clock and data recovery block. (24dB ...

Page 9

A third consecutive zero ( mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on RNRZ causes one of the following code violations: § A BPV immediately preceded by ...

Page 10

Transmitter Transmit Clock. The clock applied at the TCLK input is used to clock in data on the TPOS/TNRZ and TNEG pins. If the jitter attenuator is not enabled in the transmit path, the signal on TCLK is the ...

Page 11

Transmit Driver Monitor. If the transmit driver monitor detects a faulty transmitter, it activates the DM output pin. When the transmitter is tri-stated (TTS = 0), the transmit driver monitor is also disabled. The transmitter is declared to be faulty ...

Page 12

Table 1-E. STS-1 Waveform Template TIME (UNIT INTERVALS) -0.85 £ T £ -0.68 -0.68 £ T £ 0.26 0.26 £ T £ 1.4 -0.85 £ T £ -0.36 -0.36 £ T £ 0.36 0.36 £ T £ 1.4 Table 1-F. ...

Page 13

Figure 1-4. E3 Waveform Template 1.2 1.1 1.0 0.9 0.8 0.7 Output 0.6 Level (V) 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 Table 1-G. E3 Waveform Test Parameters and Limits PARAMETER Rate Line Code Transmission Medium Test Measurement Point ...

Page 14

Figure 1-5. DS3 AIS Structure M1 Subframe Info F1 Info C1 (1) Bits (1) Bits (0) M2 Subframe Info F1 Info C1 (1) Bits (1) Bits (0) M3 Subframe Info F1 ...

Page 15

Diagnostics PRBS Generator and Detector. The DS3150 contains on-board pseudorandom bit sequence (PRBS) generator and detector circuitry for physical layer testing. The device generates and detects unframed (DS3 or STS- generator is ...

Page 16

Jitter Attenuator The DS3150 contains an on-board jitter attenuator (JA) that can be placed in the receive path or in the transmit path or disabled. This selection is made using the RMON and TTS input pins. See selection details. ...

Page 17

PIN DESCRIPTIONS Pins are listed in alphabetical order. Section Table 2-A. Pin Descriptions NAME TYPE Active-Low Driver Monitor (Open Drain). When the transmit driver monitor detects faulty transmitter driven low. Requires an external pullup ...

Page 18

NAME TYPE PRBS Detector. The PRBS pin reports the status of the PRBS detector. The PRBS detector constantly searches for either a 2 pseudorandom bit sequence. When the PRBS detector is out of synchronization, the O3 PRBS PRBS pin is ...

Page 19

NAME TYPE Transmit Data Select Bit 1/Oscillator Frequency Select. If EFE = 1, TDS1, TDS0 and TESS select the source of the transmit data ignored. If MCLK is wired low, TDS1 is internally pulled low, and a resistor connected between ...

Page 20

Table 2-B. Transmit Data Selection TDS1 TDS0 TESS Float Transmit unframed 101010… pattern Float Transmit 2 Note: When EFE is ...

Page 21

ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V Supply Voltage Range (V ) with Respect Operating Temperature Range Storage Temperature Range Soldering Temperature Range Stresses beyond those listed under “Absolute ...

Page 22

FRAMER INTERFACE TIMING (V = 3.3V ±5 0°C to +70°C for DS3150Q/ PARAMETER RCLK/TCLK Clock Period RCLK Clock High/Low Time TCLK Clock High/Low Time TPOS/TNRZ, TNEG to TCLK Setup Time TPOS/TNRZ, TNEG Hold Time RCLK ...

Page 23

RECEIVER INPUT CHARACTERISTICS—DS3 AND STS-1 MODES (V = 3.3V ±5 0°C to +70°C for DS3150Q/ PARAMETER Receive Sensitivity (Length of Cable) Signal-to-Noise Ratio, Interfering Signal Test (Notes 9, 10) Input Pulse Amplitude, RMON = 0 ...

Page 24

TRANSMITTER OUTPUT CHARACTERISTICS—DS3 AND STS-1 MODES (V = 3.3V ±5 +70°C for DS3150Q/ PARAMETER DS3 Output Pulse Amplitude, LBO = 0 (Note 13) DS3 Output Pulse Amplitude, LBO = 1 (Note 13) STS-1 ...

Page 25

PIN CONFIGURATIONS TOP VIEW TDS1/OFSEL V SS TDS1/OFSEL TX+ ICE TX DS3150 V ...

Page 26

PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) 28-Pin PLCC Dimensions: millimeters Thermal Information +68°C/W JA DIM MIN A 0.165 ...

Page 27

TQFP Dimensions: millimeters Thermal Information +46°C/W JA DIM MIN A — A1 0.05 A2 0.95 D 8.80 D1 7.00 BSC E 8.80 E1 7.00 BSC L 0.45 E 0.50 BSC B 0. ...

Page 28

... Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation. DESCRIPTION © ...

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