DS2181AQ/T&R Maxim Integrated Products, DS2181AQ/T&R Datasheet - Page 9

IC TXRX CEPT PRIMARY RATE 44PLCC

DS2181AQ/T&R

Manufacturer Part Number
DS2181AQ/T&R
Description
IC TXRX CEPT PRIMARY RATE 44PLCC
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS2181AQ/T&R

Number Of Drivers/receivers
1/1
Protocol
CEPT
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
44-LCC, 44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS2181AQ/T&RDS2181AQ/T&R
Manufacturer:
Maxim Integrated
Quantity:
10 000
NOTE:
1. When the common channel signaling mode is enabled (TCR.5 = 1), the TSD input is disabled
CCR: COMMON CONTROL REGISTER Figure 5
(MSB)
NOTES:
1. This bit must be cleared when CRC4 multiframe mode is enabled (CCR.3 = 1); its state does not
2. CCR is considered a receive register and operates from RCLK and SCLK.
SYMBOL
internally; all timeslot 16 data is sampled at TSER.
affect CCS framing (RCR.5 = 1).
RHDE
THDE
TAFP
RCE
TCE
SAS
LLB
-
-
TAFP
POSITION
CCR.7
CCR.6
CCR.5
CCR.4
CCR.3
CCR.2
CCR.1
CCR.0
THDE
NAME AND DESCRIPTION
Reserved; must be 0 for proper operation.
Transmit Align Frame Position
When clear, the CAS multiframe begins with a frame containing
the frame alignment signal. When set, the CAS multiframe begins
with a frame not containing the frame alignment signal.
Transmit HDB3 Enable
0 = Outgoing data at TPOS and TNEG is AMI coded.
1 = Outgoing data at TPOS and TNEG is HDB3 coded.
Receive HDB3 Enable
0 = Incoming data at RPOS and RNEG is AMI coded.
1 = Incoming data is RPOS and RNEG is HDB3 coded.
Transmit CRC4 Enable
When set, outgoing international bit positions in frames 0 through
12 and 14 are replaced by CRC4 multiframe alignment and
checksum words.
Receive CRC4 Enable
0 = Disable CRC4 multiframe synchronizer.
1 = Enable CRC4 synchronizer; search for CRC4 multiframe
alignment once frame alignment complete.
Sync Algorithm Select
0 = Use old DS2181 sync algorithm
1 = Use new DS2181A sync algorithm
Local Loopback
0 = Normal operation.
1 = Internally loop TPOS, TNEG, and TCLK to RPOS, RNEG,
and RCLK.
RHDE
9 of 32
TCE
RCE
1
SAS
(LSB)
DS2181A
LLB

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