ADV7173KSTZ Analog Devices Inc, ADV7173KSTZ Datasheet - Page 35

• Manufacturer Part Number: ADV7173KSTZ
• Description: IC DAC VIDEO NTSC 6-CH 48LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7173KSTZ

• Applications: Multimedia
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 48
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7173EBM - BOARD EVAL FOR ADV7173
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TIMING REGISTER 1 (TR17–TR10)
(Address (SR4–SR0) = 0BH)
Timing Register 1 is an 8-bit-wide register.
Figure 53 shows the various operations under the control of
Timing Register 1. This register can be read from as well writ-
ten to. This register can be used to adjust the width and position
of the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulsewidth.
HSYNC to FIELD/VSYNC Delay (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
TIMING MODE 1 (MASTER/PAL)
TR17 TR16
0
0
1
1
FIELD/VSYNC
HSYNC TO PIXEL
DATA ADJUST
0
1
0
1
HSYNC
TR17
0
1
2
3
T
T
T
T
PCLK
PCLK
PCLK
PCLK
TR16
T
LINE 1
B
TR15 TR14
T
TR15 TR14
A
0
0
1
1
RISING EDGE DELAY
x
x
HSYNC TO FIELD
(MODE 1 ONLY)
(MODE 2 ONLY)
VSYNC WIDTH
TR15
0
1
0
1
0
1
1
4
16
128
T
T
B
B
+ 32 s
T
T
T
TR14
T
PCLK
PCLK
C
PCLK
T
PCLK
TR13 TR12
HSYNC to FIELD Rising Edge Delay (TR15–TR14)
When the ADV7172/ADV7173 is in Timing Mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
VSYNC Width (TR15–TR14)
When the ADV7172/ADV7173 is configured in Timing Mode
2, these bits adjust the VSYNC pulsewidth.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the pixel
data. This allows the Cr and Cb components to be swapped. This
adjustment is available in both master and slave timing modes.
TR13
0
0
1
1
FIELD/VSYNC DELAY
HSYNC TO
0
1
0
1
TR12
0
4
8
16
T
T
T
T
T
B
PCLK
PCLK
PCLK
PCLK
T
C
LINE 313
TR11
TR11 TR10
0
0
1
1
HSYNC WIDTH
0
1
0
1
TR10
LINE 314
ADV7172/ADV7173
1
4
16
128
T
T
T
A
PCLK
PCLK
T
PCLK
T
PCLK